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| lithium battery backup power assp mcu HT45FH4M revision: v1.10 date: ? an ? a ?? 1 ?? ? 01 ? ? an ? a ?? 1 ?? ? 01 ?
rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu table of contents eates cpu feat ?? es ......................................................................................................................... 6 pe ? iphe ? al feat ?? es ................................................................................................................. 6 gene?al desc?iption ........................................................................................ 7 block diag?am .................................................................................................. 7 pin assignment ........... ..................................................................................... 8 pin desc?iption .......... ...................................................................................... 9 inte ? nal connection desc ? iption .............................................................................................. 9 absol?te maxim?m ratings .......................................................................... 10 d.c. cha?acte?istics ....................................................................................... 10 a.c. cha?acte?istics ........................................................................................ 11 adc elect?ical cha?acte?istics ... .................................................................. 1? ldo reg?lato? elect?ical cha?acte?istics ................................................... 1? level conve?te? elect?ical cha?acte?istics .................................................. 1? ove? v oltage/c???ent ci?c?it elect?ical cha?acte?istics ... .......................... 1? powe? on reset elect?ical cha?acte?istics .................................................. 14 s?stem a?chitect??e ...................................................................................... 14 clocking and pipelining ......................................................................................................... 14 p ? og ? am co ? nte ? ................................................................................................................... 1 ? stack ..................................................................................................................................... 16 a ? ithmetic and logic unit C alu ........................................................................................... 16 flash p?og?am memo?? ................................................................................. 17 st ?? ct ?? e ................................................................................................................................ 17 special vecto ? s ..................................................................................................................... 17 look- ? p table ............. ........................................................................................................... 18 table p ? og ? am example ........................................................................................................ 19 in ci ? c ? it p ? og ? amming ......................................................................................................... ? 0 on-chip deb ? g s ? ppo ? t C ocds ......................................................................................... ? 1 ram data memo?? ......................................................................................... ?1 st ?? ct ?? e ................................................................................................................................ ? 1 special f?nction registe? desc?iption ........................................................ ?? indi ? ect add ? essing registe ? s C iar0 ? iar1 ......................................................................... ?? memo ?? pointe ? s C mp0 ? mp1 .............................................................................................. ?? bank pointe ? C bp ................................................................................................................. ? 4 acc ? m ? lato ? C acc ............................................................................................................... ? 4 p ? og ? am co ? nte ? low registe ? C pcl .................................................................................. ? 4 look- ? p table registe ? s C tblp ? tbhp ? tblh ..................................................................... ? 4 stat ? s registe ? C status .................................................................................................... ?? rev. 1.10 ? ?an?a?? 1?? ?01? rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu eeprom data memory ........... ....................................................................... 27 eeprom data memo ?? st ?? ct ?? e ........................................................................................ ? 7 eeprom registe ? s ............ .................................................................................................. ? 7 reading data f ? om the eeprom ........................................................................................ ? 9 w ? iting data to the eeprom ................................................................................................ ? 9 w ? ite p ? otection ..................................................................................................................... ? 9 eeprom inte ??? pt ............. ................................................................................................... ? 9 p ? og ? amming conside ? ations ............. ................................................................................... ? 0 oscillator ........................................................................................................ 31 oscillato ? ove ? view ............. .................................................................................................. ? 1 system clock confgurations ................................................................................................ ? 1 inte ? nal rc oscillato ? C hirc ............. .................................................................................. ?? inte ? nal ?? khz oscillato ? C lirc ........................................................................................... ?? operating modes and system clocks ......................................................... 32 s ? stem clocks ...................................................................................................................... ?? s ? stem ope ? ation modes ...................................................................................................... ?? cont ? ol registe ? .................................................................................................................... ?? ope ? ating mode switching .................................................................................................... ? 7 normal mode to slow mode switching ........................................................................... ? 7 slow mode to normal mode switching .......................................................................... ? 7 ente ? ing the sleep mode .................................................................................................... ? 7 ente ? ing the idle0 mode ...................................................................................................... ? 8 ente ? ing the idle1 mode ...................................................................................................... ? 8 standb ? c ??? ent conside ? ations ........................................................................................... 40 wake- ? p ................................................................................................................................ 40 watchdog timer ........... .................................................................................. 41 watchdog time ? clock so ?? ce .............................................................................................. 41 watchdog time ? cont ? ol registe ? ............. ............................................................................ 41 watchdog time ? ope ? ation ................................................................................................... 4 ? reset and initialisation .................................................................................. 43 reset f ? nctions ............. ....................................................................................................... 4 ? reset initial conditions ......................................................................................................... 46 input/output ports ......................................................................................... 49 p ? ll-high resisto ? s ................................................................................................................ 49 po ? t a wake- ? p ............. ........................................................................................................ ? 0 i/o po ? t cont ? ol registe ? s ..................................................................................................... ? 0 i/o pin st ?? ct ?? es .................................................................................................................. ? 1 p ? og ? amming conside ? ations ............. ................................................................................... ?? timer modules C tm .......... ............................................................................ 52 int ? od ? ction ........................................................................................................................... ?? tm ope ? ation ............. ........................................................................................................... ?? tm clock so ?? ce ............. ...................................................................................................... ?? tm inte ??? pts ......................................................................................................................... ?? rev. 1.10 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm exte ? nal pins ................................................................................................................... ? 4 tm inp ? t/o ? tp ? t pin cont ? ol registe ? ................................................................................... ?? p ? og ? amming conside ? ations ............. ................................................................................... ? 7 standard type tm C stm .......... .................................................................... 58 standa ? d tm ope ? ation ............. ............................................................................................ ? 8 standa ? d t ? pe tm registe ? desc ? iption ............................................................................... ? 8 standa ? d t ? pe tm ope ? ating modes .................................................................................... 6 ? periodic type tm C ptm ................................................................................ 72 pe ? iodic tm ope ? ation ............. ............................................................................................. 7 ? pe ? iodic t ? pe tm registe ? desc ? iption ................................................................................. 7 ? pe ? iodic t ? pe tm ope ? ation modes ...................................................................................... 77 analog to digital converter .......... ................................................................ 86 a/d ove ? view ............. ........................................................................................................... 86 a/d conve ? te ? registe ? desc ? iption ...................................................................................... 86 a/d conve ? te ? data registe ? s C adrl ? adrh ..................................................................... 87 a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? acerl ............................................... 87 a/d ope ? ation ....................................................................................................................... 91 a/d inp ? t pins ............. .......................................................................................................... 9 ? s ? mma ?? of a/d conve ? sion steps ............. .......................................................................... 9 ? p ? og ? amming conside ? ations ............. ................................................................................... 94 a/d t ? ansfe ? f ? nction ............. .............................................................................................. 94 a/d p ? og ? amming example ................................................................................................... 9 ? complementary pwm output ....................................................................... 97 over current and voltage protection .......................................................... 98 ocp/ovp registe ? ............................................................................................................... 99 ocp operational amplifer offset cancellation function .................................................... 104 ocp compa ? ato ? offset cancellation f ? nction .................................................................. 10 ? ovp compa ? ato ? offset cancellation f ? nction ................................................................... 10 ? interrupts ...................................................................................................... 106 inte ??? pt registe ? s ............................................................................................................... 106 inte ??? pt registe ? contents ............. .................................................................................... 106 inte ??? pt ope ? ation ............................................................................................................... 111 exte ? nal inte ??? pt ............. ..................................................................................................... 11 ? ovp inte ??? pt ....................................................................................................................... 11 ? ocp inte ??? pt ....................................................................................................................... 11 ? m ? lti-f ? nction inte ??? pt ......................................................................................................... 114 a/d conve ? te ? inte ??? pt ........................................................................................................ 114 time base inte ??? pts ............................................................................................................ 114 eeprom inte ??? pt ............. .................................................................................................. 116 lvd inte ??? pt ........................................................................................................................ 116 tm inte ??? pts ........................................................................................................................ 116 inte ??? pt wake- ? p f ? nction ................................................................................................. 117 p ? og ? amming conside ? ations ............. .................................................................................. 117 rev. 1.10 4 ?an?a?? 1?? ?01? rev. 1.10 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu low voltage detector C lvd .......... .............................................................. 118 lvd registe ? ............. ........................................................................................................... 118 lvd ope ? ation ...................................................................................................................... 119 application circuits ........... .......................................................................... 120 instruction set .............................................................................................. 121 int ? od ? ction ......................................................................................................................... 1 ? 1 inst ?? ction timing ................................................................................................................ 1 ? 1 moving and t ? ansfe ?? ing data ............................................................................................. 1 ? 1 a ? ithmetic ope ? ations .......................................................................................................... 1 ? 1 logical and rotate ope ? ations ............. ............................................................................... 1 ?? b ? anches and cont ? ol t ? ansfe ? ........................................................................................... 1 ?? bit ope ? ations ..................................................................................................................... 1 ?? table read ope ? ations ....................................................................................................... 1 ?? othe ? ope ? ations ............. .................................................................................................... 1 ?? instruction set summary .......... .................................................................. 123 instruction defnition ................................................................................... 125 package information ................................................................................... 134 ? 0-pin sop ( ? 00mil) o ? tline dimensions ........................................................................... 1 ? 4 ? 0-pin ssop (1 ? 0mil) o ? tline dimensions ......................................................................... 1 ?? reel dimensions ................................................................................................................. 1 ? 6 ca ?? ie ? tape dimensions ..................................................................................................... 1 ? 7 rev. 1.10 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu features cpu features ? operating v oltage: f sys = 7.5 mhz: 2. 7v~5.5v f sys = 15mhz: 4.5v~5.5v ? up to 0.27s instruction cycle with 15mhz system clock at v dd = 5v ? power down and wake-up functions to reduce power consumption ? oscillators: internal rc -- hirc internal 32khz -- lirc ? fully intergrated internal 30mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 4-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k16 ? ram data memory: 1288 ? eeprom memory: 648 ? watchdog t imer function ? up to 13 bidirectional i/o lines ? two pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output function or single pulse output function ? over current protection (ocp) with interrupt ? over voltage protection (ovp) with interrupt ? dual t ime-base functions for generation of fxed time interrupt signals ? 8-channel 12-bit resolution a/d converter ? low voltage reset function (enable@2.55v) ? low voltage detect function ? one integrated ldo: 5v output ? 2 level shift output pins ? package : 20-pin ssop rev. 1.10 6 ?an?a?? 1?? ?01? rev. 1.10 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu general description the device is a flash memory type 8-bit high performance risc architecture microcontroller . offering users the convenience of flash memory multi-programming features, th is device also include s a wi de ra nge of func tions a nd fe atures. ot her m emory i ncludes a n a rea of ram da ta memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-cha nnel 12-bit a/d converter , an over voltage protection function, an over current protection function and a ldo regulator . multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise imm unity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of h irc and lirc os cillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vice wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. block diagram ovp rev. 1.10 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu pin assignment 1 3 2 4 6 5 8 7 12 11 15 16 13 14 2 pa 2/ an 2 pa 0/ ovp / an 0 pa 1/ dapwr / an 1/ vref vdd vss pa / int 0/ tck 0/ an pa / an pa / ocp / an 0/ 0 1 ht 45 fh 4m 20 ssop -a pb 7 pb 6 10 9 18 17 19 20 ax / bx vcc cx / dx 1/ 1 1 v vss pa / int 1/ tck 1/ an / icpda / ocdsda pa / 0 0/ an / icpck / ocdsck HT45FH4M 20 ssop-a note: 1. the HT45FH4M i/o lines, pb5/outl, pb4/outh and pb3/tp1_0, are internally connected to the level shift inputs, a, c and enbf , respectively. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. 3. the 20ssop-a package is for the real ic, the 20sop-a package is for the ocds ev ic. rev. 1.10 8 ?an?a?? 1?? ?01? rev. 1.10 9 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu pin description with the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their port name, e.g. p a.0, p a.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function opt i/t o/t pin-shared mapping pa0~pa7 gene ? al p ?? pose i/o po ? t a papu pawu st cmos pb0~pb ?? pb6~pb7 gene ? al p ?? pose i/o po ? t b pbpu st cmos ovp ove ? voltage p ? otection inp ? t ocvpr1 an pa0 ocp ove ? c ??? ent p ? otection inp ? t ocvpr1 an pa ? dapwr d/a conve ? te ? powe ? inp ? t ocvpr0 pwr pa1 an0~an7 a/d conve ? te ? inp ? t 0~7 adcr0 acerl an pa0~pa7 vref a/d conve ? te ? ? efe ? ence voltage inp ? t adcr1 an pa1 int0 ? int1 exte ? nal inte ??? pt 0 ? 1 integ intc0 intc ? st pa ?? pa6 tck0 ? tck1 tm0 ? tm1 inp ? t st pa ?? pa6 tp0_0 ? tp0_1 tm0 i/o tmpc st cmos pa7 ? pb0 tp1_1 tm1 i/o tmpc st cmos pb1 icpck in-ci ? c ? it p ? og ? amming clock pin st pa7 icpda in-ci ? c ? it p ? og ? amming data/add ? ess pin st cmos pa6 ocdsck on-chip deb ? g s ? ppo ? t clock pin st pa7 ocdsda on-chip deb ? g s ? ppo ? t data/add ? ess pin st cmos pa6 v ? ? v ldo o ? tp ? t pwr vcc ? v ldo powe ? s ? ppl ? and level shift o ? tp ? t d ? iving powe ? pwr vdd positive powe ? s ? ppl ? pwr vss negative powe ? s ? ppl ?? g ? o ? nd pwr ax ? bx ? cx ? dx level shift o ? tp ? ts internal connection description signal name function opt i/t o/t pin-shared mapping pb ? ~pb ? gene ? al p ?? pose inp ? t/o ? tp ? t. registe ? enabled p ? ll- ? p. inte ? nall ? connected to the level shift inp ? ts ? espectivel ? and level shift enable. pbpu st cmos outl ? outh pwm o ? tp ? t inte ? nall ? connected to the level shift inp ? ts a and c tmpc cmos pb4 ? pb ? a ? c level shift inp ? ts inte ? nall ? connected to pb ? /outl and pb4/outh ? espectivel ? enbf level shift enable inte ? nall ? connected to pb ? /tp1_0 note: i/t: input type; o/t: output type opt : optional by confguration option (co) or register option pwr: power; st: schmitt t rigger input cmos: cmos output; an: analog signal rev. 1.10 10 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu absolute maximum ratings supply v oltage ........................ v ss -0.3v to v ss +6.0v input v oltage ........................... v ss -0.3v to v dd +0.3v i ol t otal ............................................................... 80ma total power dissipation ................................... 500mv storage t emperature .......................... -50c to 150c operating t emperature ........................ -40c to 85c i oh t otal ............................................................. -80ma note: these are stress ratings only . stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not impl ied and prolonged exposure to extreme conditions may af fect device reliability. d.c. characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage f sys = 7. ? mhz ? .7 ? . ? v f sys = 1 ? mhz 4 . ? ? . ? v i dd1 ope ? ating c ??? ent ? no ? mal mode ? f h = ? 0mhz ? v no load ? f sys = f h / ?? adc off ? wdt enable ? . ? ? .0 ma ? v 7. ? 11. ? ma ? v no load ? f sys = f h /4 ? adc off ? wdt enable ? .4 ? .60 ma ? v ? .4 8.10 ma ? v no load ? f sys = f h /8 ? adc off ? wdt enable ? ? .00 ma ? v 4. ? 6. ? 0 ma ? v no load ? f sys = f h /16 ? adc off ? wdt enable 1.8 ? .70 ma ? v ? .6 ? .40 ma ? v no load ? f sys = f h / ??? adc off ? wdt enable 1.6 ? .40 ma ? v ? . ? 4.80 ma ? v no load ? f sys = f h /64 ? adc off ? wdt enable 1.6 ? .4 ma ? v ? . ? 4.8 ma i dd ? ope ? ating c ??? ent ? slow mode ? f sys = f sub = lirc ? ? v no load ? f sys = lirc ? adc off ? wdt enable 10 ? 0 ? v ? 0 ? 0 i idle01 idle0 mode stanb ? c ??? ent (lirc on) ? v no load ? adc off ? wdt enable ? lvr disable 1. ? ? .0 ? v ? . ? ? .0 i idle11 idle1 mode stanb ? c ??? ent ? v no load ? adc off ? wdt enable ? f sys = ? 0mhz on ? .0 ? .0 ma ? v 4.0 6.0 ma i sleep sleep mode stanb ? c ??? ent (lirc on) ? v no load ? adc off ? wdt enable ? lvr disable 1. ? ? .0 ? v ? . ? ? .0 v il1 inp ? t low voltage fo ? i/o po ? ts o ? inp ? t pins ? v 0 1. ? v 0 0. ? v dd v v ih1 inp ? t high voltage fo ? i/o po ? ts o ? inp ? t pins ? v ? . ? ? .0 v 0.8v dd v dd v i ol1 i/o po ? t sink c ??? ent (pa ? pb0~pb ?? pb6 ? pb7) ? v v ol = 0.1v dd 6.4 1 ? .8 ma ? v v ol = 0.1v dd 16 ?? ma i oh1 i/o po ? t so ?? ce c ??? ent (pa ? pb0~pb ?? pb6 ? pb7) ? v v oh = 0.9v dd ? .4 4.8 ma ? v v oh = 0.9v dd 6 1 ? ma i ol ? i/o po ? t sink c ??? ent (pb4 ? pb ? ) ? v v ol = 0.1v dd 8 16 ma ? v v ol = 0.1v dd ? 0 40 ma rev. 1.10 10 ?an?a?? 1?? ?01? rev. 1.10 11 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu symbol parameter test conditions min. typ. max. unit v dd conditions i oh ? i/o po ? t so ?? ce c ??? ent (pb4 ? pb ? ) ? v v oh = 0.9v dd -8 -16 ma ? v v oh = 0.9v dd - ? 0 -40 ma v lvr low voltage reset voltage - ? % t ? p. ? . ?? - ? % t ? p. v v lvd1 low voltage detecto ? voltage lvden= 1 ? v lvd = ? . 7v - ? % t ? p. ? .7 - ? % t ? p. v v lvd ? lvden= 1 ? v lvd = ? .0v ? .0 v v lvd ? lvden= 1 ? v lvd = ? . ? v ? . ? v v lvd4 lvden= 1 ? v lvd = ? .6 v ? .6 v v lvd ? lvden= 1 ? v lvd = 4.0v 4.0 v i lvr additional powe ? cons ? mption if lvr is ? sed ? v lvr enable ? 0 4 ? a ? v 60 90 a i lvd additional powe ? cons ? mption if lvd is ? s ed ? v lvd disable lvd enable (lvr enable) ? 0 4 ? a ? v 60 90 a r ph p ? ll-high resistance fo ? i/o po ? ts ? v ? 0 60 100 k ? v 10 ? 0 ? 0 k ote: lvr is aways enabled halt mode disabled) fed2.55v. a.c. characteristics 7d & symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? .7 v ~ ? . ? v dc 7. ? mhz 4. ? v ~ ? . ? v dc 1 ? mhz f sys s ? stem clock (hirc) ? .7 v ~ ? . ? v 7. ? mhz 4. ? v ~ ? . ? v 1 ? mhz f hirc hirc f ? eq ? enc ? (note) ? v ta= ?? c - ? % ? 0 + ? % mhz 4.0v ~ ? . ? v ta= -10c~8 ? c - ? % ? 0 + ? % mhz ? .6v ~ ? . ? v ta= -40c~8 ? c -10% ? 0 +10% mhz f sub s ? stem clock (lirc) ? v ta= ?? c -10% ?? +10% khz ? .7 v~ ? . ? v ta= -40c ~ 8 ? c - ? 0% ?? +60% khz t timer tckn inp ? t pin minim ? m p ? lse width ? 0 ns t int inte ??? pt minim ? m p ? lse width 1 ? . ? ? s t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to inte ??? pt ? 0 4 ? 90 s t lvds lvdo stable time fo ? lvr enable ? lvd off on 1 ? s t sreset softwa ? e reset width to reset 4 ? 90 1 ? 0 s t eerd eeprom read time ? 4 t sys t eewr eeprom w ? ite time ? 4 ms t sst s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om halt ? f sys off at halt state) f sys = hirc 16 t sys f sys = lirc ? t sys s ? stem sta ? t- ? p time ? pe ? iod (wake- ? p f ? om halt ? f sys on at halt state) ? t sys rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu symbol parameter test conditions min. typ. max. unit v dd conditions t rstd s ? stem reset dela ? time (powe ? on reset) ?? ? 0 100 ms s ? stem reset dela ? time (an ? reset except powe ? on reset) 8. ? 16.7 ?? . ? ms note: 1. t sys = 1/f sys ; t sub = 1/f sub 2. t o maintain the accuracy of the internal hirc oscillator frequency , a 0.1f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. adc electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v adi a/d conve ? te ? inp ? t voltage 0 v ref v v ref a/d conve ? te ? refe ? ence voltage ? v dd v v bg refe ? ence voltage - ? % 1. ?? + ? % v dnl diffe ? ential non-linea ? it ? ? v t adck v 1 ? lsb inl integ ? al non-linea ? it ? ? v t adck v ? 4 lsb i adc additional powe ? cons ? mption if a/d conve ? te ? is ? sed ? v no load (t adck v 0.9 1. ?? ma ? v no load (t adck v 1. ? 1.8 ma i bg additional powe ? cons ? mption if v bg refe ? ence with b ? ffe ? is ? sed ? 00 ? 00 t adck a/d conve ? te ? clock pe ? iod 0. ? 10 v t adc a/d conve ? sion time (incl ? de sample and hold time) 1 ? bit adc 16 t adck t ads a/d conve ? te ? sampling time 4 t adck t on ? st a/d conve ? te ? on-to-sta ? t time ? v t bgs v bg t ?? n on stable time ? 00 v ldo regulator electrical characteristics v5= 5v, v in = v out + 1.0v, i o = 1ma, t a= 25c, unless otherwise specifed symbol parameter test conditions min. typ. max. unit 9 out o ? tp ? t voltage tole ? ance i o =10ma ? ta= ?? c - ? ? %/v 9 load load reg ? lation (note 1) p? o p 0.09 0.18 %/ma v drop d ? op o ? t voltage (note ? ) i o = 1ma ? 9 o = ? % 100 mv i ss q ? ienscent c ??? ent i o = 0ma ? 4 v line line reg ? lation 99 out 9 in 9 i o = 1ma 0. ? %/v v in inp ? t voltage v cc ? 8 v 9 out 7d 7hpshudwxuh&rhiflhqw i o = 10ma ? -40 c < ta< 8 ? c 0.9 mv/c note: 1. load regulation is measure d at a constant junction temperatu re, using pulse testing with a low on time and i s gua ranteed up t o t he m aximum powe r di ssipation. powe r di ssipation i s de termined by t he i nput/ output dif ferential vol tage and the out put current. guarant eed ma ximum power dissi pation wil l not be available o ver t he f ull i nput/output r ange. t he m aximum a llowable p ower d issipation a t a ny a mbient temperature is p d = (t j(max) -ta)/ ja. 2. dropout voltage is defned as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at v in = v out +2v. rev. 1.10 1? ?an?a?? 1?? ?01? rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu level converter electrical characteristics v cc = 12v, t a= 25c, unless otherwise specifed symbol parameter test conditions min. typ. max. unit v dd conditions i so ?? ce o ? tp ? t so ?? ce c ??? ent of ax ? bx ? cx ? dx v oh = 10.4v -60 -90 ma i sink o ? tp ? t sink c ??? ent of ax ? bx ? cx ? dx v ol = 1.6v 60 90 ma over v oltage/current circuit electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions i ocvp ove ? c ??? ent/voltage p ? otection ope ? ation c ??? ent ? v ocpen= 1 ? ovpen= 1 ? 00 ? 00 ? v 4 ? 0 600 compartor (ca, cb) v cmpos1 compa ? ato ? inp ? t offset voltage ? v / ? v witho ? t calib ? ation caof[ ? :0] ? cbof[ ? :0]=100000b -1 ? +1 ? mv v cmpos ? compa ? ato ? inp ? t offset voltage ? v / ? v with calib ? ation -4 +4 mv v hys h ? ste ? esis width ? v / ? v ? 0 40 60 mv v cm compa ? ato ? common mode voltage ? ange ? v / ? v v ss v dd - 1.4v v a ol compa ? ato ? open loop gain ? v / ? v 60 80 db t pd compa ? ato ? ? esponse time ? v / ? v with 100mv ove ? d ? ive ? 70 ? 60 ns opa (a) v opos1 inp ? t offset voltage ? v / ? v witho ? t calib ? ation ? aof[ ? :0]=100000b -1 ? 1 ? mv v opos ? inp ? t offset voltage ? v / ? v with calib ? ation -4 +4 mv v cm compa ? ato ? common mode voltage ? ange ? v / ? v v ss v dd - 1.4v v psrr powe ? s ? ppl ? rejection ratio ? v / ? v 60 80 db cmrr common mode rejetion ratio ? v / ? v 60 80 db sr slew ? ate + ? slew ? ate - ? v / ? v 1.8 ? . ? 9s gbw gain band width ? v / ? v ? 00 khz dac for ocpref/ovpref dnl dac diffe ? ential nonlinea ? it ? -1 +1 lsb inl dac integ ? al nonlinea ? it ? - ? + ? lsb rev. 1.10 14 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu power on reset electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd sta ? t voltage to e ns ?? e powe ? -on reset 100 mv r por vdd rising rate to e ns ?? e powe ? -on reset 0.0 ?? v/ms t por minim ? m time fo ? v dd sta ? s at v por to ens ?? e powe ? -on reset 1 ms system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the m ain syst em c lock, de rived from e ither an hirc or l irc osc illator i s subdi vided i nto four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. rev. 1.10 14 ?an?a?? 1?? ?01? rev. 1.10 1 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ? ? ? ? ? ? ?? system clock and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications. ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl7~pcl0 rev. 1.10 16 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 17 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.10 16 ?an?a?? 1?? ?01? rev. 1.10 17 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, th is flash device of fer s users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. ? ? ? ? ? ? ?? ? ? - ? ? - ? - program memory structure rev. 1.10 18 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 19 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the tabrd [ m] o r tabrdl[m] i nstructions, r espectively. w hen t he i nstruction i s e xecuted, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table. instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [m] @10 @9 @8 @7 @6 @ ? @4 @ ? @ ? @1 @0 tabrdl [m] 1 1 1 @7 @6 @ ? @4 @ ? @ ? @1 @0 table location note: b10~b0 : t able location bits @7~@0: t able pointer (tblp) bits @10~@8: t able pointer (tbhp) bits rev. 1.10 18 ?an?a?? 1?? ?01? rev. 1.10 19 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa6 p ? og ? amming se ? ial data/add ? ess icpck pa7 p ? og ? amming clock vdd vdd powe ? s ? ppl ? vss vss g ? o ? nd during the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu on-chip debug support C ocds an ev chip exists for the purposes of device emulation. this ev chip device also provides an on-chip de bug fu nction t o de bug t he de vice du ring t he de velopment pr ocess. t he e v c hip and t he a ctual mc u de vices a re a lmost func tionally c ompatible e xcept for t he on-chip de bug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip deb ? g s ? ppo ? t data/add ? ess inp ? t/o ? tp ? t ocdsck ocdsck on-chip deb ? g s ? ppo ? t clock inp ? t vdd vdd powe ? s ? ppl ? gnd vss g ? o ? nd ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu 00h iar 0 01h mp 0 0?h iar 1 0?h mp 1 04h 0?h acc 06h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh smod 0 ch lvdc 0 dh integ 0 eh 0 fh 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac un?sed 1?h 14h mfi 0 1?h mfi 1 16h 17h : un?sed ? ?ead as 00h intc ? mfi ? pbc wdtc tbc pbpu pb ctrl adrl adrh adcr 0 adcr 1 acerl un?sed tm 0c0 tm 0c1 tm 0 dl tm 0 dh tm 0 al tm 0 ah tm 0 rp tm 1c1 ?0h ?1h ??h ?9 h ?8 h ? bh ? ah ? dh ? ch ? fh ? eh ??h ?4h ??h ?6h ?7h ?0 h ?1 h ?? h ? dh ? ch ? fh ? eh ?? h ?4 h ?? h ?6 h ?7 h tm 1 dl tm 1 dh tm 1 al tm 1 ah ocpref 40 h 41 h 4? h 4? h 44 h 4? h 46 h 47 h 48 h 49 h 4 ah 7 fh bp tmpc un?sed lvrc tm 1c0 tm 1r pl tm 1 rp h : ocvpr 0 ocvpr 1 ocvpr ? cpr un?sed : : : : un?sed 1 eh eea eed bank 0 ? 1 bank 0 bank 1 eec ovpref ocvpr ? ocvpr 4 ocvpr ? special purpose data memory structure 00h 7fh 80h ffh special p??pose data memo?? gene?al p??pose data memo?? data memory structure rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu bank pointer C bp for this device, the data memory is divided into two banks , bank0 and bank1 . selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addre ssing the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank 1 must be implemented using indirect a ddressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 b it 7 ~ 1 unimplemented, read as "0" b it 0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter s a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" ? nknown b it 7 ~ 6 unimplemented, read as "0" b it 5 : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. b it 4 : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction b it 3 : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. b it 2 : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero b it 1 : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction b it 0 : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation is also affected by a rotate through carry instruction. rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ? 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 648 bits. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d ? d4 d ? d ? d1 d0 eed d7 d6 d ? d4 d ? d ? d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as "0" b it 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0 rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as "0" b it 3 : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. b it 2 : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. b it 1 : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. b it 0 : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applicat ion program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples ? reading data from the eeprom - polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eed ; move read data to register mov read_data, a ? writing data to the eeprom - polling method clr emi mov a, eeprom_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit set emi back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options an d registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the watchdog t imer and t ime base interrupts. f ully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. inte ? nal high speed rc hirc ? 0mhz inte ? nal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. the high speed oscillator is the internal 30mhz rc oscillator . the low speed oscillator is t he i nternal 32 khz (l irc) osc illator. se lecting whe ther t he l ow or hi gh spe ed osc illator i s use d as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the high speed and the low speed oscillators is chosen via a combination of confguration options an d registers . the frequency of the slow speed or high speed sys tem clock is also determined us ing the h lclk bit and ck s2 ~ ck s0 bits in the s mod regis ter. n ote that tw o oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. high speed oscillato? hirc lirc low speed oscillato? f h 6-stage p?escale? hlclk? cks?~cks0 bits f h /? f h /4 f h /8 f h /16 f h /?? f h /64 f sub f sys system clock confgurations rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has several frequencies of either 30mhz by option . device trimming during the manufa cturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperat ure and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation . internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from the hirc oscillator . the low speed system clock source can be sourced from the lirc osc illator. t he ot her c hoice, wh ich i s a di vided ve rsion of t he hi gh sp eed system oscillator has a range of f h /2~f h /64. rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ? ? ? ? ? ? ? - ? ? ?? - ?? ? ? system clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. system operation modes there a re f ive d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remaining three modes, the sleep , idle0 a nd i dle1 mo de, a re u sed wh en t he m icrocontroller c pu i s swi tched o ff t o c onserve p ower. operating mode description cpu f sys f sub f tbc normal mode on f h ~f h /64 on on slow mode on f sub on on ilde0 mode off off on on idle1 mode off on on on sleep mode off off on off rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. t he c lock so urce u sed wi ll b e f rom f sub . r unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod regis ter is low . in the s leep mode the cp u w ill be s topped. h owever the f sub clock w ill continue to operate. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl register i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped , the low frequency f sub will be on. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the low frequency f sub will be on. note: if l vden=1 and the sleep or idle mode is entered, the l vd and bandgap functions will not be disabled, and the f sub clock will be forced to be enabled. rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 1 1 0 0 0 1 0 b it 7 ~ 5 : the system clock selection when hlclk is 0 000: f sub 001: f sub 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0. b it 3 : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscill ator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles. b it 2 : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. t herefore t his fag wi ll a lways b e r ead a s 1 by the application program after device power -on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. b it 1 : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. b it 0 : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f sub cloc k is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 b it 7 : f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0. bit 2 : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 b ? the wdt cont ? ol ? egiste ? softwa ? e ? eset and clea ? ed b ? the application p ? og ? am. note that this bit can onl ? be clea ? ed to 0 b ? the application p ? og ? am. ? ? ? ?? ? ? ? ? ?? ? ? ? rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ? 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/ slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000b or 001b in the smod register .this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto b it i s c hecked. t he a mount o f t ime r equired f or h igh sp eed sy stem o scillator st abilization depends upon which high speed system oscillator type is used. entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruc tion, but the t ime base clock f tbc and the low frequency f sub will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock together with the t ime base clock f tbc and the low frequency f sub will be on and the application program will stop at the halt instruc tion. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ?? ? ?? ? ? ? ?? ? ?? ? ? ? ?? ? ?? ? ? ?? ???? ? ? ? ? ?? ???? ? ? ? ? ?? ???? rev. 1.10 40 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 41 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow i f the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. t he actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a sys tem power -up or executing the clear w atchdog t imer instructions and is set w hen executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake- up that only resets the program counter and stack pointer , the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. rev. 1.10 40 ?an?a?? 1?? ?01? rev. 1.10 41 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal f sub clock which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 t o 2 18 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc register. t he lirc internal oscillator has an approximate period of 32 khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wdtc register is initiated to 0101001 1b at any reset but keeps unchanged at the wdt time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101 or 01010: enabled other: reset mcu when these bits are changed by the environmental noise to reset the microcontroller , the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1. bit 2~0 : wdt t ime-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 4? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys cont ? ol in idle mode desc ? ibe elsewhe ? e. bit 6~ ? : unimplemented ? ? ead as 0 bit ? lvrf : lvr function reset fag describe elsewhere. bit 1 lrf : lvr control register software reset fag describe elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the w dt control register software reset and c leared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. t here are fve bits, we4~we0, in the wdtc register to enable the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. we4 ~ we0 bits wdt function 01010b o ? 10101b enable an ? othe ? val ? e reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b a nd 10101b, t he se cond i s usi ng t he w atchdog t imer soft ware c lear i nstructions a nd t he third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.10 4? ?an?a?? 1?? ?01? rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu clr wdtinst??ction 8-stage divide? wdt p?escale? we4~we0 bits wdtc registe? reset mcu lirc f sub f sub /? 8 8-to-1 mux clr ws?~ws0 (f sub /? 8 ~ f sub /? 18 ) wdt time-o?t (? 8 /f sub ~ ? 18 /f sub ) watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the watchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. vdd powe?-on reset sst time-o?t t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart rev. 1.10 44 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 4? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low su pply v oltage st ate d oes n ot e xceed t his v alue, t he l vr wi ll i gnore t he l ow su pply v oltage and wi ll n ot p erform a r eset f unction. t he a ctual v lvr i s fx ed a t a v oltage v alue o f 2 .55v b y t he lvs bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise, the l vr will reset the device after 2~3 lirc cloc k cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. note:t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs ? lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 lvs7 ~ lvs0: lvr voltage select 01010101: 2.55v 00110011: 2.55v 10011001: 2.55v 10101010: 2.55v any other value: generates mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by the above defned l vr voltage value, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles . in this s ituation this regis ter contents w ill remain the same after such a reset occurs. any register value, other than the four defined values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation this register contents will be reset to the por value. rev. 1.10 44 ?an?a?? 1?? ?01? rev. 1.10 4 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f control in idle mode describe elsewhere. bit 6~3 : unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 wrf 7&rwurouhjlvwhuvriwzduhuhvhwdj desc ? ibe elsewhe ? e. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t details. note: the t is 15~16 clock cycles if the system clock source is provided by the hirc. the t is 1~2 clock for the lirc. wdt time-out reset during sleep or idle timing chart rev. 1.10 46 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 47 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset ? ? lvr ? eset d ?? ing normal o ? slow mode ope ? ation 1 ? wdt time-o ? t ? eset d ?? ing normal o ? slow mode ope ? ation 1 1 wdt time-o ? t ? eset d ?? ing idle o ? sleep mode ope ? ation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? am co ? nte ? reset to ze ? o inte ??? pts all inte ??? pts will be disabled wdt clea ? afte ? ? eset ? wdt begins co ? nting time ? mod ? les time ? mod ? les will be t ?? ned off inp ? t/o ? tp ? t po ? ts i/o po ? ts will be set ? p as inp ? ts and an0~an7 as a/d inp ? t pins stack pointe ? stack pointe ? will point to the top of the stack rev. 1.10 46 ?an?a?? 1?? ?01? rev. 1.10 47 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle ) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- --- ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- -xxx ---- - ??? ---- - ??? ---- - ??? status --00 xxxx --1 ? ???? -- ? ? ???? --11 ???? smod 110- 0010 110- 0010 110- 0010 ? ?? - ???? lvdc --00 -000 --00 -000 --00 -000 -- ?? - ??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? -000 -000 -000 -000 -000 -000 - ??? - ??? mfi0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi1 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi ? --00 --00 --00 --00 --00 --00 -- ?? -- ?? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pawu 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0000 0000 0000 0000 0000 ???? ???? tmpc 1100 0000 1100 0000 1100 0000 ???? ???? wdtc 0101 0011 0101 0011 0101 0011 ???? ???? tbc 0011 -111 0011 -111 0011 -111 ???? - ??? eea --00 0000 --00 0000 --00 0000 -- ?? ???? eed 0000 0000 0000 0000 0000 0000 ???? ???? eec ---- 0000 ---- 0000 ---- 0000 ---- ???? adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- ???? adcr0 0110 0000 0110 0000 0110 0000 ???? ???? adcr1 00-0 -000 00-0 -000 00-0 -000 ?? - ? - ??? rev. 1.10 48 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 49 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu register reset (power on) wdt time-out (normal operation) lvr reset wdt time-out (sleep/idle ) acerl 1111 1111 1111 1111 1111 1111 ???? ???? ctrl 0--- -x00 0--- -000 0--- -000 ? --- - ??? lvrc 0101 0101 0101 0101 0101 0101 ???? ???? tm0c0 0000 0--- 0000 0--- 0000 0--- ???? ? --- tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh 0000 0000 0000 0000 0000 0000 ???? ???? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah 0000 0000 0000 0000 0000 0000 ???? ???? tm0rp 0000 0000 0000 0000 0000 0000 ???? ???? tm1c0 0000 0--- 0000 0--- 0000 0--- ???? ? --- tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1rpl 0000 0000 0000 0000 0000 0000 ???? ???? tm1rph ---- --00 ---- --00 ---- --00 ---- -- ?? cpr ---0 0000 ---0 0000 ---0 0000 --- ? ???? ocpref 0000 0000 0000 0000 0000 0000 ???? ???? ovpref --00 0000 --00 0000 --00 0000 -- ?? ???? ocvpr0 0000 0000 0000 0000 0000 0000 ???? ???? ocvpr1 000- 0000 000- 0000 000- 0000 ??? - ???? ocvpr ? 0010 0000 0010 0000 0010 0000 ???? ???? ocvpr ? 0010 0000 0010 0000 0010 0000 ???? ???? ocvpr4 0010 0000 0010 0000 0010 0000 ???? ???? ocvpr ? ---- -xxx ---- -xxx ---- -xxx ---- - ??? note: "-" not implement u stands for unchanged x stands for unknown rev. 1.10 48 ?an?a?? 1?? ?01? rev. 1.10 49 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a and pb. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d ? d4 d ? d ? d1 d0 pac d7 d6 d ? d4 d ? d ? d1 d0 papu d7 d6 d ? d4 d ? d ? d1 d0 pawu d7 d6 d ? d4 d ? d ? d1 d0 pb d7 d6 d ? d4 d ? d ? d1 d0 pbc d7 d6 d ? d4 d ? d ? d1 d0 pbpu d7 d6 d ? d4 d ? d ? d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers p apu~pbpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port b bit 7 ~ bit 0 pull-high control 0: disable 1: enable rev. 1.10 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?1 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to w ake-up the microcontroller , one of w hich is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its ow n control regis ter know n as p ac~pbc, to control the input/output configuration. w ith this control regi ster, eac h cmos out put or input can be reconfigured dynamically un der sof tware c ontrol. e ach p in o f t he i/ o p orts i s di rectly m apped t o a b it i n i ts associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 ~ 0 i/o port b bit 7 ~bit 0 input/output control 0: output 1: input rev. 1.10 ?0 ?an?a?? 1?? ?01? rev. 1.10 ? 1 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ?? ? ?? ? ? ? generic input/output structure ? ? ? ? ? ? - ? ? - ? ?? ? a/d input/output structure rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pbc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pb, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming individual b its i n t he p ort c ontrol r egister u sing t he set [ m].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. read/wite timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual standard and periodic tm section. introduction the de vice c ontains a 16-bi t st andard t m a nd a 10-bi t pe riodic t m, e ach t m ha ving a re ference name of t m0 a nd t m1. al though si milar i n na ture, t he di fferent t m t ypes va ry i n t heir fe ature complexity. the common features to the standard and periodic tms will be described in this section and the detailed operation will be described in corresponding sections. the main features of the standard tm are summarised in the accompanying table. rev. 1.10 ?? ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu function stm ptm time ? /co ? nte ? i/p capt ?? e compa ? e match o ? tp ? t pwm channels 1 1 single p ? lse o ? tp ? t 1 1 pwm alignment edge edge pwm adj ? stment pe ? iod & d ? t ? d ? t ? o ? pe ? iod d ? t ? o ? pe ? iod tm function summary tm0 tm1 16-bit stm 10-bit ptm tm name/type reference tm operation the two different t ypes o f t m s o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin cloc k source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the two different types of tms have two internal interrupts, the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. rev. 1.10 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each ha ve one or two output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must firs t be setup using registers. a single bit in one of the registers determines if its associated pi n i s t o be use d a s a n e xternal t m out put pi n or i f i t i s t o ha ve a nother func tion. the number of output pins for each tm type is dif ferent, the details are provided in the accompanying table. s tm and ptm output pin names have an _n suffx. pin names that include a _ 0 or _ 1 suffx indicate that they are from a tm with multiple output pins. thi s allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tm0 tm1 tp0_0 ? tp0_1 tp1_1 tm output pins note: the tp1_0 signal is pin-shared with the pb3 and only used to be internally connected to the level shift enable control input and is not bonded to the external tm output pin. rev. 1.10 ?4 ?an?a?? 1?? ?01? rev. 1.10 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. tm0 function pin control block diagram ? tm1 function pin control block diagram rev. 1.10 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tmpc register register name bit 7 6 5 4 3 2 1 0 name outhn outln outcp1 outcp0 t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 0 0 0 0 0 0 bit 7 outhn : outh signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the outh signal is inverted or not before output. bit 6 outln : outl signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the outl signal is inverted or not before output. bit 5~4 outcp [1:0] : outh and outl pin control 00: normal i/o function, i.e., pb5 and pb4 01: pb5 and outh 10: outl and pb4 11: outl and outh if thes e bits are set to 1 1, the dead time circuitry w ill be automatically enabled. if t hese bi ts a re se t t o a val ue e xcept 11, t hen t he dea d t ime c ircuitry wi ll be automatically disabled. bit 3 t1cp1 : tp1_1 pin control 0: tp1_1 pin is disabled 1: tp1_1 pin is enabled bit 2 t1cp0 : tp1_0 pin control 0: tp1_0 pin is disabled 1: tp1_0 pin is enabled note that the tp1_0 pin which is pin-shared with i/o line pb3 is internally connected to the level shift enable control input and the tp1_0 pin function can not be used. bit 1 t0cp1 : tp0_1 pin control 0: tp0_1 pin is disabled 1: tp0_1 pin is enabled bit 0 t0cp0 : tp0_0 pin control 0: tp0_0 pin is disabled 1: tp0_0 pin is enabled rev. 1.10 ?6 ?an?a?? 1?? ?01? rev. 1.10 ? 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu programming considerations the tm counter registers, the capture/compare ccra registers and the tm1 ccrp registers, being eith er 16-bit or 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specific way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra or ccrp low byte registers, named tmxal or tmxrpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. ? ? ? the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmxal or tmxrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmxdh, tmxah or tmxrph C he re da ta i s re ad di rectly from t he hi gh byt e re gisters a nd si multaneously da ta i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxrpl C this step reads data from the 8-bit buffer. rev. 1.10 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 ?9 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive two external output pins. these two external output pins can be the same signal or the inverse signal. name tm no. tm input pin tm output pin 16-bit stm 0 tck0 tp0_0 ? tp0_1 ? ?? ? ? ? ? ? ? ? ? ? ? -?? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ? ? ? ? ? standard type tm block diagram (n=0) standard tm operation at its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is 8- bits wide whose value is compared with the highest 8 bits in the counter while the ccra is the 16 bits and therefore compares with all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear the counter by changing the t 0 on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. standard type tm register description overall operation of the standard tm is controlled using seven registers. a read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes. rev. 1.10 ?8 ?an?a?? 1?? ?01? rev. 1.10 ? 9 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm0c0 t0pau t0ck ? t0ck1 t0ck0 t0on tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d6 d ? d4 d ? d ? d1 d0 tm0dh d1 ? d14 d1 ? d1 ? d11 d10 d9 d8 tm0al d7 d6 d ? d4 d ? d ? d1 d0 tm0ah d1 ? d14 d1 ? d1 ? d11 d10 d9 d8 tm0rp d7 d6 d ? d4 d ? d ? d1 d0 16-bit standard tm register list tm0c0 register bit 7 6 5 4 3 2 1 0 name t0pau t0ck ? t0ck1 t0ck0 t0on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 : tm0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6 ~ 4 : select tm0 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. b it 3 : tm0 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit change s from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high. b it 2 ~ 0 unimplemented, read as 0 rev. 1.10 60 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 61 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm0c1 register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 6 : select tm 0 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the bits. in the t imer/ counter mode, the tm output pin control must be disabled. b it 5 ~ 4 : select tm 0 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: force inactive state 01: force active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tm capture input pin 01: input capture at falling edge of tm capture input pin 10: input capture at falling/rising edge of tm capture input pin 11: input capture disabled timer/counter mode: unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t 0 io1 ~ t 0 io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the t 0io1~t0io0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit . note that the output level requested by the t 0io1~t0 io0 bits must be dif ferent from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. af ter t he t m o utput p in c hanges st ate i t c an b e r eset t o i ts i nitial l evel b y changing the level of the t0on bit from low to high. in the pwm mode, the t 0 io1 and t 0 io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by changing t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t 0 io1 and t 0 io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t 0 io1 and t 0 io0 bits are changed when the tm is running. rev. 1.10 60 ?an?a?? 1?? ?01? rev. 1.10 61 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu b it 3 t0oc : tm 0 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. b it 2 t0pol : tm 0 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tm output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. b it 1 t0dpx : tm 0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. b it 0 t0cclr : select tm 0 counter clear condition 0: tm comparatror p match 1: tm comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t 0 cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t 0 cclr bit is not used in the pwm, single pulse or input capture mode. name d7 d6 d ? d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm0dl : tm 0 counter low byte register bit 7 ~ bit 0 tm 16-bit counter bit 7 ~ bit 0 name d1 ? d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 b it 7 ~ 0 tm0dh : tm 0 counter high byte register bit 7 ~ bit 0 tm 16-bit counter bit 15 ~ bit 8 rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 6? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm0al register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 : tm 0 ccra low byte register bit 7 ~ bit 0 tm 16-bit ccra bit 7 ~ bit 0 tm0ah register bit 7 6 5 4 3 2 1 0 name d1 ? d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 : tm 0 ccra high byte register bit 7 ~ bit 0 tm 16-bit ccra bit 15 ~ bit 8 tm0rp register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 : tm 0 ccr p high byte register bit 7 ~ bit 0 tm0 ccrp 8-bit register, compared with the tm0 counter bit 15 ~ bit 8. comparator p match period 0: 65536 tm0 clocks 1~255: 256 (1~255) tm0 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be selected t o c lear t he i nternal c ounter i f t he t 0 cclr bi t i s se t t o zero. set ting t he t 0 cclr bi t t o zero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o overfl ow a t its maximum value. rev. 1.10 6? ?an?a?? 1?? ?01? rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t0m1 and t0m0 bits in the tm0c1 register. compare output mode to select this mode, bits t 0 m1 and t 0 m0 in the tm 0 c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t 0 cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the counter to overflow . h ere both t 0 af and t 0 pf interrupt request flags for comparator a and comparator p respectively, will both be generated. if the t 0 cclr bit in the tm 0 c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t 0 af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t 0 cclr i s h igh n o t 0 pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t 0 af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 0 pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t0 io1 and t 0 io0 bits in the tm 0 c1 register . the tm output pin can be selected using the t 0 io1 and t 0 io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t0 on bit changes from low to high, is setup using the t 0 oc bit. note that if the t 0 io1 and t 0 io0 bits are zero then no pin change will take place. rev. 1.10 64 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 6? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ccra ccrp 0xffff co?nte? ove?flow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 co?nte? clea?ed b? ccrp val?e tm o/p pin tnon pa?se co?nte? reset o?tp?t pin set to initial level low if tnoc = 0 o?tp?t toggle with tnaf flag he?e tnio1? tnio0 = 11 toggle o?tp?t select now tnio1? tnio0 = 10 active high o?tp?t select o?tp?t not affected b? tnaf flag. remains high ?ntil ?eset b? tnon bit tncclr = 0; tnm[1:0] = 00 tnpau res?me stop time ccrp > 0 ccrp = 0 tnpol o?tp?t pin reset to initial val?e o?tp?t inve?ts when tnpol is high o?tp?t cont?olled b? othe? pin-sha?ed f?nction co?nte? val?e compare match output mode -- tncclr = 0 note: 1. w ith tncclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the o utput pin reset to initial state by a tnon bit rising edge 4. n = 0 rev. 1.10 64 ?an?a?? 1?? ?01? rev. 1.10 6 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ccrp ccra 0xffff ccra = 0 co?nte? ove?flows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 co?nte? clea?ed b? ccra val?e tm o/p pin tnon pa?se co?nte? reset o?tp?t pin reset to initial val?e o?tp?t pin set to initial level low if tnoc = 0 o?tp?t toggle with tnaf flag he?e tnio1? tnio0 = 11 toggle o?tp?t select now tnio1? tnio0 = 10 active high o?tp?t select tnpau res?me stop time tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow o?tp?t does not change ccra = 0 o?tp?t inve?ts when tnpol is high tnpol tncclr = 1; tnm[1:0] = 00 o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t not affected b? tnaf flag ?emains high ?ntil ?eset b? tnon bit co?nte? val?e compare match output mode -- tncclr = 1 note: 1. w ith tncclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fags is not generated when tncclr = 1 5. n = 0 rev. 1.10 66 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 67 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu timer/counter mode to select this mode, bits t 0 m1 and t 0 m0 in the tm 0 c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t 0 m1 and t 0 m0 in the tm 0 c1 register should be set to 10 respectively and also the t 0 io1 and t 0 io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 0 cclr bi t ha s no e ffect a s t he pw m period. both of the ccraand ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t 0 dpx bit in the tm 0 c1 register. the pw m wa veform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t 0 oc bit in the tm 0 c1 register is used to select the required polarity of the pwm waveform while the two t0 io1 and t 0 io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t 0 pol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm mode, edge-aligned mode, t 0dpx=0 ccrp 1~255 0 pe ? iod ccrp ?? 6 6 ??? 6 d ? t ? ccra if f sys = 7.5mhz, tm clock source is f sys /4, ccrp = 2 and ccra =128, the stm pwm output frequency = (f sys /4)/ 512 = f sys /2048 = 3.66khz, duty = 128/ 512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stm, pwm mode, edge-aligned mode, t 0dpx=1 ccrp 1~255 0 pe ? iod ccra d ? t ? ccrp ?? 6 6 ??? 6 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0. rev. 1.10 66 ?an?a?? 1?? ?01? rev. 1.10 67 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ccrp ccra co?nte? val?e co?nte? clea?ed b? ccrp ccra int. flag tnaf ccrp int. flag tnpf tm o/p pin tnoc = 1 tnon co?nte? stop if tnon bit low co?nte? ?eset when tnon ?et??ns high pwm ?es?mes ope?ation time tnpol o?tp?t inve?ts when tnpol = 1 tm o/p pin tnoc = 0 tnpau res?me pa?se tndpx = 0 ; tnm [1:0] = 10 o?tp?t cont?olled b? othe? pin - pwm pe?iod set b? ccrp pwm d?t? c?cle set b? ccra pwm mode -- tndpx = 0 note: 1. here tndpx = 0 - counter cleared by ccrp 2. a c ounter c lear sets pwm period 3. the i nternal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 rev. 1.10 68 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 69 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu a ccrp co?nte? val?e co?nte? clea?ed b? ccr a ccra int. flag tnaf ccrp int. flag tnpf tm o/p pin tnoc = 1 tnon co?nte? stop if tnon bit low co?nte? ?eset when tnon ?et??ns high pwm ?es?mes ope?ation time tnpol o?tp?t inve?ts when tnpol = 1 tm o/p pin tnoc = 0 tnpau res?me pa?se tndpx = 1 ; tnm [1:0] = 10 o?tp?t cont?olled b? othe? pin - pwm pe?iod set b? ccr a pwm d?t? c?cle set b? ccr p pwm mode -- tndpx = 1 note: 1. here tndpx = 1 - counter cleared by ccra 2. a c ounter c lear sets pwm period 3. the i nternal pwm function continues even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 single pulse mode to se lect t his mode , bit s t 0 m1 and t 0 m0 i n t he t m 0 c1 regi ster should be se t t o 10 respe ctively and also the t 0 io1 and t 0 io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t 0 on bit, which can be implemented using the application program. however in the single pulse mode, the t 0 on bit can also be made to automatically change from low to high using the external tck 0 pin, which will in turn initiate the single pulse output. when the t 0 on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t 0 on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t 0 on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. rev. 1.10 68 ?an?a?? 1?? ?01? rev. 1.10 69 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ? ? ? ? ? ? ? ? ? ? ? single pulse generation (n= 0) ccra ccrp ccrp int . flag tnpf ccra int . flag tnaf tm o/p pin tnoc = 1 tnon set b? ccra tnio 1 ? tnio0 = 11 no ccrp inte???pt gene?ated co?nte? stops b? softwa?e co?nte? ?eset when tnon ?et??ns high time tnpol o?tp?t inve?ts when tnpol = 1 tm o/p pin tnoc = 0 tnpau res?me pa?se softwa?e t?igge? tcn pin clea?ed b? ccra match tckn pin t?igge? a?to. set b? tckn pin softwa?e clea? softwa?e t?igge? softwa?e t?igge? tnm [1:0] = 10; tnio [1:0] = 11 co?nte? val?e b? ccra tnio 1 ? tnio0 = 11 single p?lse o?tp?t tnio 1 ? tnio0 = 00 softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the p ulse is triggered by the tckn pin or setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n = 0 rev. 1.10 70 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 71 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu however a compare match from comparator a will also automatically clear the t 0 on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t 0 on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t 0 cclr and t 0 dpx bits are not used in this mode. capture input mode to s elect this mode bits t 0 m1 and t 0 m0 in the tm 0 c1 regis ter s hould be s et to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tp 0 _0 or tp 0 _1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t 0 io1 and t 0 io0 bits in the tm 0 c1 regis ter. the counter is s tarted w hen the t 0 on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp 0 _0 or tp 0 _1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp 0 _0 or tp 0 _1 pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of ov erflow i nterrupt si gnals fro m t he cc rp c an be a use ful m ethod i n m easuring l ong pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tp 0 _0 or tp 0 _1 pin to be a ris ing edge, falling edge or both edge types . if the tnio 1 and tnio 0 bits are both s et high, then no capture operation will take place irrespective of what happens on the tp 0 _0 or tp 0 _1 pin, however it must be noted that the counter will continue to run. as the tp 0 _0 or tp 0 _1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t 0 cclr and t 0 dpx bits are not used in this mode. rev. 1.10 70 ?an?a?? 1?? ?01? rev. 1.10 71 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ccrp co?nte? val?e co?nte? ove?flow ccrp int. flag tnpf ccra int. flag tnaf tnon pa?se co?nte? reset tnpau res?me stop time yy xx ccra val?e xx tm capt??e pin tpn_x yy tnio [1:0] val?e 00 - rising edge 01 - falling edge 11 - disable capt??e active edge active edge xx 10 - both edges edge yy tnm [1:0] = 01 active capture input mode note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function - tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0 rev. 1.10 7 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 7? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with an external input pin and can drive one external output pin. periodic tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the t1on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers. ? ? ? ? ? ? ?? ? - ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ?? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? periodic type tm block diagram (n=1) periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. rev. 1.10 7? ?an?a?? 1?? ?01? rev. 1.10 7 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1capts t1cclr tm1dl d7 d6 d ? d4 d ? d ? d1 d0 tm1dh d9 d8 tm1al d7 d6 d ? d4 d ? d ? d1 d0 tm1ah d9 d8 tm1rpl d7 d6 d ? d4 d ? d ? d1 d0 tm1rph d9 d8 10-bit periodic tm register list tm1c0 register bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 : tm 1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. b it 6 ~ 4 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: f h 110: tck 1 rising edge clock 111: tck 1 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. b it 3 : tm 1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit change s from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. bit 2~0 unimplemented, read as 0 rev. 1.10 74 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 7? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm1c1 register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1capts t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0 : select tm1 operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t1m1 and t1m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1 01: input capture at falling edge of tp1_0, tp1_1 01: input capture at falling/rising edge of tp1_0, tp1_1 11: input capture disabled timer/counter mode unused. these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t 1io1 a nd t 1io0 bi ts de termine how t he tm out put pin change s sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch hi gh, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register . note that the output level requested by the t1io1 and t1io0 bits must be dif ferent from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t1io1 and t1io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running. rev. 1.10 74 ?an?a?? 1?? ?01? rev. 1.10 7 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu bit 3 t1oc : tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 and tp1_1 output pins. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t1capts : tm1 capture trigger source select 0: from tp1 pin 1: from tck1 pin bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm mode, single pulse or input capture mode. tm1dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7 ~ bit 0 tm1 10-bit counter bit 7 ~ bit 0 tm1dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 : unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter low byte register bit 1 ~ bit 0 tm1 10-bit counter bit 9 ~ bit 8 rev. 1.10 76 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 77 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tm1al register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7 ~ bit 0 tm1 10-bit ccra bit 7 ~ bit 0 tm1ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 : unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra low byte register bit 1 ~ bit 0 tm1 10-bit ccra bit 9 ~ bit 8 tm1rpl register bit 7 6 5 4 3 2 1 0 name d7 d6 d ? d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1rpl : tm1 ccrp low byte register bit 7 ~ bit 0 tm1 10-bit ccrp bit 7 ~ bit 0 tm1rph register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 : unimplemented, read as 0 bit 1~0 tm1rph : tm1 ccrp low byte register bit 1 ~ bit 0 tm1 10-bit ccrp bit 9 ~ bit 8 rev. 1.10 76 ?an?a?? 1?? ?01? rev. 1.10 77 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu periodic type tm operation modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t1m1 and t1m0 bits in the tm1c1 register. compare match output mode to select this mode, bits t1m1 and t1m0 in the tm1c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t1cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t 1af a nd t 1pf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the t1cclr bit in the tm1c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t1af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t1cclr i s h igh n o t 1pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t1af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 1pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t1io1 and t1io0 bits in the tm1c1 register . the tm output pin can be selected using the t1io1 and t1io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t1on bit changes from low to high, is setup using the t1oc bit. note that if the t1io1 and t1io0 bits are zero then no pin change will take place. rev. 1.10 78 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 79 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu co?nte? val?e 0x?ff ccrp ccra t1on t1pau t1pol ccrp int. flag t1pf ccra int. flag t1af tm o/p pin time ccrp=0 ccrp > 0 co?nte? ove?flow ccrp > 0 co?nte? clea?ed b? ccrp val?e pa?se res?me stop co?nte? resta?t t1cclr = 0; t1m [1:0] = 00 o?tp?t pin set to initial level low if t1oc=0 o?tp?t toggle with t1af flag note t1io [1:0] = 10 active high o?tp?t select he?e t1io [1:0] = 11 toggle o?tp?t select o?tp?t not affected b? t1af flag. remains high ?ntil ?eset b? t1on bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when t1pol is high compare match output mode C t1cclr=0 note: 1. w ith t1cclr=0 C a comparator p match will clear the counter 2. the tm output pin is controlled only by the t1af fag 3. the output pin is reset to its initial state by a t1on bit rising edge rev. 1.10 78 ?an?a?? 1?? ?01? rev. 1.10 79 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu co?nte? val?e 0x?ff ccrp ccra t1on t1pau t1pol ccrp int. flag t1pf ccra int. flag t1af tm o/p pin time ccra=0 ccra = 0 co?nte? ove?flow ccra > 0 co?nte? clea?ed b? ccra val?e pa?se res?me stop co?nte? resta?t t1cclr = 1; t1m [1:0] = 00 o?tp?t pin set to initial level low if t1oc=0 o?tp?t toggle with t1af flag note t1io [1:0] = 10 active high o?tp?t select he?e t1io [1:0] = 11 toggle o?tp?t select o?tp?t not affected b? t1af flag. remains high ?ntil ?eset b? t1on bit o?tp?t pin reset to initial val?e o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when t1pol is high t1pf not gene?ated no t1af flag gene?ated on ccra ove?flow o?tp?t does not change compare match output mode C t1cclr=1 note: 1. w ith t1cclr=1 C a comparator a match will clear the counter 2. the tm output pin is controlled only by the t1af fag 3. the output pin is reset to its initial state by a t1on bit rising edge 4. a t1pf fag is not generated when t1cclr=1 rev. 1.10 80 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 81 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu timer/counter mode to select this mode, bits t1m1 and t1m0 in the tm1c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t1m1 and t 1m0 i n t he t m1c1 regi ster shoul d be se t t o 10 respe ctively and also the t1io1 and t1io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control, etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 1cclr bi t ha s no e ffect a s t he pw m period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t1oc bit in the tm1c1 register is used to select the required polarity of the pwm waveform while the two t1io1 and t1io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t1pol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm mode period duty ccrp ccra if f sys =7.5mhz, tm clock source select f h , ccrp = 100 and ccra=40, the ptm pwm output frequency = f h /100=300khz, duty=40/100=40% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. rev. 1.10 80 ?an?a?? 1?? ?01? rev. 1.10 81 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu co?nte? val?e ccrp ccra t1on t1pau t1pol ccrp int. flag t1pf ccra int. flag t1af tm o/p pin (t1oc=1) time co?nte? clea?ed b? ccrp pa?se res?me co?nte? stop if t1on bit low co?nte? reset when t1on ?et??ns high t1m [1:0] = 10 pwm d?t? c?cle set b? ccra pwm ?es?mes ope?ation o?tp?t cont?olled b? othe? pin-sha?ed f?nction o?tp?t inve?ts when t1pol = 1 pwm pe?iod set b? ccrp tm o/p pin (t1oc=0) pwm mode note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when t1io [1:0] = 00 or 01 4. the t1cclr bit has no infuence on pwm operation rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 8? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu single pulse output mode to se lect t his mode , bit s t1m1 and t 1m0 i n t he t m1c1 regi ster shoul d be se t t o 10 respe ctively and also the t1io1 and t1io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t1on bit, which can be implemented using the application program. however in the single pulse mode, the t1on bit can also be made to automatically change from low to high using the external tck1 pin, which will in turn initiate the single pulse output. when the t1on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t1on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t1on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the t1on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t1on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t1cclr is not used in this mode. ? ? ? ? ? ?? ? ? ?? single pulse generation rev. 1.10 8? ?an?a?? 1?? ?01? rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu co?nte? val?e ccrp ccra t1on t1pau t1pol ccrp int. flag t1pf ccra int. flag t1af tm o/p pin (t1oc=1) time co?nte? stopped b? ccra pa?se res?me co?nte? stops b? softwa?e co?nte? reset when t1on ?et??ns high t1m [1:0] = 10 ; t1io [1:0] = 11 p?lse width set b? ccra o?tp?t inve?ts when t1pol = 1 no ccrp inte???pts gene?ated tm o/p pin (t1oc=0) tck1 pin softwa?e t?igge? clea?ed b? ccra match tck1 pin t?igge? a?to. set b? tck1 pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tck1 pin or by setting the t1on bit high 4. a tck1 pin active edge will automatically set the t1on bit high 5. in the single pulse mode, t1io [1:0] must be set to 11 and can not be changed. rev. 1.10 84 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 8? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu capture input mode to s elect this mode bits t1m1 and t1m0 in the tm 1c1 regis ter s hould be s et to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tp1 or tck1 pin, selected by the t1capts bit in the tm1c0 register . the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t1io1 and t1io0 bits in the tm1c1 register . the counter is started when the t1on bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tp1 or tck1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp1 or tck1 pin the counter will continue to free run until the t1on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the t1io1 and t1io0 bits can select the active trigger edge on the tp1 or tck1 pin to be a rising edge, falling edge or both edge types. if the t1io1 and t1io0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp1 or tck1 pin, however it must be noted that the counter will continue to run. as the tp1 or tck1 pin is pin shared with other functions, care must be taken if the tm1 is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t1cclr, t1oc and t1pol bits are not used in this mode. rev. 1.10 84 ?an?a?? 1?? ?01? rev. 1.10 8 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu co?nte? val?e yy ccrp t1on t1pau ccrp int. flag t1pf ccra int. flag t1af ccra val?e time co?nte? clea?ed b? ccrp pa?se res?me co?nte? reset t1m [1:0] = 01 tm capt??e pin tp1 o? tck1 xx co?nte? stop t1io [1:0] val?e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capt??e capture input mode note: 1. t1m [1:0] = 01 and active edge set by the t1io [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. t1cclr bit not used 4. no output function C t1oc and t1pol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. rev. 1.10 86 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 87 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. input channels a/d channel select bits input pins 8 acs4 ? acs ? ~acs0 an0~an7 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. ?? ? ? ? ? ?? ? - ? ? ? ???? ? ?? ? ? ? ? ? ?? ? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing fve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d ? d ? d1 d0 adrl(adrfs=1) d7 d6 d ? d4 d ? d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d ? d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs ? acs ? acs1 acs0 adcr1 acs4 vbgen vrefs adck ? adck1 adck0 acerl ace7 ace6 ace ? ace4 ace ? ace ? ace1 ace0 a/d converter register list rev. 1.10 86 ?an?a?? 1?? ?01? rev. 1.10 87 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d ? d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d ? d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 a nd acerl a re provide d. t hese 8-bi t re gisters de fne func tions such a s t he sel ection of which analog channel is connected to the internal a /d converter , the digitis ed data format, the a / d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs4~acs0 bits to determine which analog channel input signals or internal 1.25v is actually connected to the internal a/d converter. the acerl control register contains the ace7~ace0 bits which determine which pins on port a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corres ponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. rev. 1.10 88 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 89 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs ? acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 b it 7 : start the a/d conversion 0 1 0: start 0 1: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. b it 6 : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. b it 5 : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff= 1 before entering idle/sleep mode for saving power. 2. adoff= 1 will power down the adc module. b it 4 : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. b it 3 ~ 0 : select a/d channel (when acs4 is 0) 0 000: an0 0 001: an1 0 010: an2 0 011: an3 0 100: an4 0 101: an5 0 110: an6 0 111: an7 1xxx: an8 ( from opa output for ocp ) these are the a/d channel select control bits. as there is only one internal hardware a/ d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the intern al 1.25v will be routed to the a/d converter. rev. 1.10 88 ?an?a?? 1?? ?01? rev. 1.10 89 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 vbgen vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 : selecte internal 1.25v as adc input control 0: disable 1: enable this b it e nables 1.25v t o b e c onnected t o t he a/ d c onverter. t he vbgen b it m ust frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. b it 6 : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap 1.25v voltage can be used by the a/d converter . if 1.25v is not used by the a/d converter and the l vr/lvd function is disabled then the bandgap reference circuit will be automatically sw itched of f to conserve power . when 1.25v is switched on for use by the a/d converter , a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. b it 5 unimplemented, read as "0" b it 4 : selecte adc reference voltage 0: internal adc power 1: v ref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high then the a/d converter reference voltage is supplied on the external v ref pin. if the pin is low then the internal referenc e is used which is taken from the power supply pin vdd. b it 3 unimplemented, read as "0" b it 2 ~ 0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. rev. 1.10 90 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 91 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace ? ace4 ace ? ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7 : defne p a7 is a/d input or not 0: not a/d input 1: a/d input, an7 b it 6 : defne p a6 is a/d input or not 0: not a/d input 1: a/d input, an6 b it 5 : defne pa 5 is a/d input or not 0: not a/d input 1: a/d input, an5 b it 4 : defne pa 4 is a/d input or not 0: not a/d input 1: a/d input, an4 b it 3 : defne pa 3 is a/d input or not 0: not a/d input 1: a/d input, an3 b it 2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 b it 1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 b it 0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 rev. 1.10 90 ?an?a?? 1?? ?01? rev. 1.10 91 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be out of the recommended a/d clock period range. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s ? s 4s 8s 16s* ?? s* 64s* undefned ? mhz ? 00ns 1s ? s 4s 8s 16s* ?? s* undefned 4mhz ?? 0ns* ? 00ns 1s ? s 4s 8s 16s* undefned 8mhz 1 ?? ns* ?? 0ns* ? 00ns 1s ? s 4s 8s undefned 1 ? mhz 8 ? ns* 167ns* ??? ns* 667ns 1. ?? s ? .67 s ? . ?? s undefned 16mhz 6 ? . ? ns* 1 ?? ns* ?? 0ns* ? 00ns 1s ? s 4s undefned ? 0mhz ? 0ns* 100ns* ? 00ns* 400ns* 800ns 1.6s ? . ? s undefned a/d clock period examples rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace7~ace0 bits in the acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically . a/d input pins all of t he a/ d a nalog i nput pi ns a re pi n-shared wi th t he i/ o pi ns on por t a a s we ll a s ot her functions. the ace7~ace0 bits in the acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace7~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup t hrough register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the ace7~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref . ? ? ? ? ? ? ?? ? - ? a/d input structure rev. 1.10 9? ?an?a?? 1?? ?01? rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace7~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade , must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr 0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period. rev. 1.10 94 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 9? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? - a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain s a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref )/4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage= a/d output digital value (v dd or v ref )/4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level. ? ? ? ? ? ? ?? ? ? ? ideal a/d transfer function rev. 1.10 94 ?an?a?? 1?? ?01? rev. 1.10 9 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st example, t he m ethod o f p olling t he e ocb b it i n t he adcr0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. ? example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr a doff mov a ,0fh ; setup acerl to confgure pins an0~an3 mov a cerl,a mov a ,0 1 h mov a dcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz e ocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : jmp start_conversion ; start next a/d conversion rev. 1.10 96 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 97 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ? example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a ,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr a doff mov a ,0fh ; setup acerl to confgure pins an0~an3 mov ac erl,a mov a ,0 1 h mov a dcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr start ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti rev. 1.10 96 ?an?a?? 1?? ?01? rev. 1.10 97 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu complementary pwm output the device provides a complementary output pair of signals which can be used as a pwm driver signal. the signal is sourced from the tm1 output signal, tp1. for pmos type upper side driving, the pwm output is an active low signal while for nmos type lower side driving the pwm output is an active high signal. when these complementary pwm outputs are both used to drive the upper and low sides, the dead time generator will automatically be enabled and a dead time, which is programmable us ing the d tpsc and d t bits in the cp r register , w ill be inserted to prevent excessive d c currents . the dead time w ill be inserted whenever the rising edge of the dead time generator i nput si gnal o ccurs. w ith a d ead t ime i nsertion, t he o utput si gnals a re e ventually se nt out to the external power transistors. the dead time generator will only be enabled if both of the complementary outputs are used, as determined by the outcp bits in the tmpc register. tp1 dead time generator dtpsc [1:0] prescaler f h a b dt [2:0] e c d pwmh (driving upper side pmos, active low) pwml (driving lower side nmos, active high) f d outcp [1:0] complementary pwm output block diagram tp1 a b c d e dead time dead time dead time dead time dead time dead time complementary pwm output waveform rev. 1.10 98 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 99 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu cpr register bit 7 6 5 4 3 2 1 0 name dtpsc1 dtpsc0 dt ? dt1 dt0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 5 unimplemented, read as 0 b it 4 ~ 3 : dead time prescaler division ratio select 00: f d =f h /1 01: f d =f h /2 10: f d =f h /4 11: f d =f h /8 b it 2 ~ 0 : dead time select 000: dead time is [(1/f d )-(1/f h )] ~ (1/f d ) 001: dead time is [(2/f d )-(1/f h )] ~ (2/f d ) 010: dead time is [(3/f d )-(1/f h )] ~ (3/f d ) 011: dead time is [(4/f d )-(1/f h )] ~ (4/f d ) 100: dead time is [(5/f d )-(1/f h )] ~ (5/f d ) 101: dead time is [(6/f d )-(1/f h )] ~ (6/f d ) 110: dead time is [(7/f d )-(1/f h )] ~ (7/f d ) 111: dead time is [(8/f d )-(1/f h )] ~ (8/f d ) over current and voltage protection th e device includes an over voltage and over current protection function w hich provides a protection mechanism for the battery charge and discharge applications. ? ovp protection to prevent the output voltage from exceeding 5.4v , the ovp input voltage is compared with a reference voltage generated by a 6-bit d/a converter . the 6-bit d/a converter power is supplied by the external power pin named dapwr. once the ovp input voltage is greater than the reference voltage, it will force the outh and outl signals inactive, i.e., the outh signal will be forced into a high state and the outl signal will be forced into a low state before the polarity control, to turn the external mos off for over voltage protection. ? ocp protection to prevent the possibility of large battery current s , the ocp input volta ge from the battery sense resistor is compar ed with a referenc e voltage generated by an 8-bit d/a converter . the 8-bit d/ a converter power is supplied by the external power pin named dapwr. once the ocp input voltage is greater than the reference voltage, it will force the outh and outl signals inactive, i.e., the outh signal will be forced into a high state and the outl signal will be forced into a low state before the polarity control, to turn the external mos off for over current protection. the outh and outl signals can be forced to an inactive state when either an over voltage or an over current event oc curs. if an over voltage or an over current event occurs, the corresponding interrupt will be generated. once the over voltage or over current condition has disappeared, the outh and outl signals will recover to drive the pwm output. the operational amplifer in the over current protection circuitry can be confgured in an inverting or non-inverting opa confguration to sense the battery current when the battery is undergoing a charge or dischar ge operation. it is recommended that the op a should be in a non-inverting mode during a charge operation and in an in verting mode during a discharge operation. more informat ion for the out h and out l si gnal polari ty and output cont rol is desc ribed in the tmpc register. rev. 1.10 98 ?an?a?? 1?? ?01? rev. 1.10 99 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu r 1? r 8 bit dac ocp ( inte???pt & flag ) to adc inp?t ( an 8) opamc a cb ca to adc dapwr 6 bit d/a ocpr [7:0] ovp ( inte???pt & flag ) ovp 1 en pwmh ovp 0 en ocp 1 en ocp 0 en ovpr [?:0] ovp ocp outhn m u x 0 tp 1 inve?te? o? non - inve?te? opa outcp 1 outcp 0 1 m u x 0 1 pwml tp 1 outh l.s outln outl l.s cx/ dx ax/ bx over voltage and over current protection block diagram ocp/ovp register overall operation of the over current and over voltage protection is controlled using several registers. t wo registers are used to provide the reference voltages for the over current and over voltage protection respectively . there are three registers which are used to cancel out the operational amplifier and comparator input of fset. a register exists to store the operational amplifier output status as a logical condition. the remaining registers are control registers which control the ocp/ ovp function, pin function, output status together with the hysteresis function. for a more detailed description regarding the input of fset voltage cancellation procedures, refer to the corresponding application notes on the holtek website. register name bit 7 6 5 4 3 2 1 0 ocpref ocpr7 ocpr6 ocpr ? ocpr4 ocpr ? ocpr ? ocpr1 ocpr0 ovpref ovpr ? ovpr4 ovpr ? ovpr ? ovpr1 ovpr0 ocvpr0 ocpen ovpen ocp1en ocp0en ovp1en ovp0en chyben chyaen ocvpr1 opamc ovpc ocpc dbb1 dbb0 dba1 dba0 ocvpr ? aofm ars aof ? aof4 aof ? aof ? aof1 aof0 ocvpr ? caofm cars caof ? caof4 caof ? caof ? caof1 caof0 ocvpr4 cbofm cbrs cbof ? cbof4 cbof ? cbof ? cbof1 cbof0 ocvpr ? ax cbx cax ocp/ovp register lists rev. 1.10 100 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 101 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ocpref register bit 7 6 5 4 3 2 1 0 name ocpr7 ocpr6 ocpr ? ocpr4 ocpr ? ocpr ? ocpr1 ocpr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 ~ 0 : over current protection reference voltage select ocp reference voltage = (dapwr/256)ocpr, where ocpr is the ocpref register content in decimal notation . ovpref register bit 7 6 5 4 3 2 1 0 name ovpr ? ovpr4 ovpr ? ovpr ? ovpr1 ovpr0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as 0 b it 5 ~ 0 : over voltage protection reference voltage select ovp reference voltage = (dapwr/64)ovpr, where ovpr is the ovpref register content in decimal notation . ocvpr0 register bit 7 6 5 4 3 2 1 0 name ocpen ovpen ocp1en ocp0en ovp1en ovp0en chyben chy aen r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 : over current protection function enable control 0: disable 1: enable if the ocpen bit is cleared to 0, the over current protection function is disabled and no power will be consumed . this results in the operational amplifer , comparator and d/a converter all being switched off. bit 6 : over v oltage protection function enable control 0: disable 1: enable if the ovpen bit is cleared to 0, the over voltage protection function is disabled and no power will be consumed . this results in the comparator and d/a converter all being switched off. bit 5 : outl over current protection enable control 0: disable 1: enable this b it i s u sed t o c ontrol wh ether t he out l si gnal i s f orced i n to a n i nactive st ate when an over current condition occurs. if the ocpen and ocp1en bits both are set to 1, the outl signal will be forced inactive when an over current condition occurs. if the outl signal protection function is disabled by clearing the ocp1en bit to 0, the outl signal will not be affected when an over current condition occurs. rev. 1.10 100 ?an?a?? 1?? ?01? rev. 1.10 101 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu bit 4 ocp0en : outh over current protection enable control 0: disable 1: enable this bi t i s use d t o c ontrol whe ther t he outh signal i s force d i n to a n i nactive st ate when an over current condition occurs. if the ocpen and ocp0en bits both are set to 1, the outh signal will be forced inactive when an over current condition occurs. if the outh signal protection function is disabled by clearing the ocp0en bit to 0, the outh signal will not be affected when an over current condition occurs. bit 3 ovp1en : outl over v oltage protection enable control 0: disable 1: enable this b it i s u sed t o c ontrol wh ether t he out l si gnal i s f orced i n to a n i nactive st ate when an over voltage condition occurs. if the ovpen and ovp1en bits both are set to 1, the outl signal will be forced inactive when an over voltage condition occurs. if the outl signal protection function is disabled by clearing the ovp1en bit to 0, the outl signal will not be affected when an over voltage condition occurs. bit 2 ovp0en : outh over v oltage protection enable control 0: disable 1: enable this bi t i s use d t o c ontrol whe ther t he outh signal i s force d i n to a n i nactive st ate when an over voltage condition occurs. if the ovpen and ovp0en bits both are set to 1, the outh signal will be forced inactive when an over voltage condition occurs. if the outh signal protection function is disabled by clearing the ovp0en bit to 0, the outh signal will not be affected when an over voltage condition occurs. bit 1 chyben : over current protection comparator hysteresis enable control 0: disable 1: enable bit 0 chyaen : over v oltage protection comparator hysteresis enable control 0: disable 1: enable rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 10? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ocvpr1 register bit 7 6 5 4 3 2 1 0 name opamc ovpc ocpc dbb1 dbb0 dba1 dba0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bi t 7 opamc : over current protection operational amplifer mode control 0: invert mode 1: non- invert mode bit 6 ovpc : over v oltage protection pin control 0: ovp pin is disabled 1: ovp pin is enabled bit 5 ocpc : over current protection pin control 0: ocp pin is disabled 1: ocp pin is enabled bit 4 unimplemented, read as 0. bit 3~2 dbb1~dbb0 : over current protection comparator debounce t ime select 00: no debounce 01: debounce time = (15~16) 1/f 10: debounce time = (31~32) 1/f 11: debounce time = (63~64) 1/f bit 1~0 dba1~dba0 : over v oltage protection comparator debounce t ime select 00: no debounce 01: debounce time = (15~16) 1/f 10: debounce time = (31~32) 1/f 11: debounce time = (63~64) 1/f ocvpr2 register bit 7 6 5 4 3 2 1 0 name aofm ars aof ? aof4 aof ? aof ? aof1 aof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 aofm : over current protection operational amplifer input offset v oltage cancellation mode selec 0: operational amplifer mode 1: input offset v oltage cancellation mode bit 6 ars : over current protection operational amplifer offset v oltage cancellation reference input select 0: operational amplifer negative input selected 1: operational amplifer positive input selected bit 5~0 aof5~aof0 : operational amplifer input v oltage offset cancellation setting rev. 1.10 10? ?an?a?? 1?? ?01? rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ocvpr3 register bit 7 6 5 4 3 2 1 0 name caofm cars caof ? caof4 caof ? caof ? caof1 caof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 caofm : over v oltage protection comparator input offset v oltage cancellation mode select 0: comparator mode 1: input offset v oltage cancellation mode bit 6 cars : over v oltage protection comparator offset v oltage cancellation reference input select 0: comparator negative input selected 1: comparator positive input selected bit 5~0 caof5~caof0 : over v oltage protection comparator input v oltage offset cancellation ocvpr4 register bit 7 6 5 4 3 2 1 0 name cbofm cbrs cbof ? cbof4 cbof ? cbof ? cbof1 cbof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 cbofm : over current protection comparator input offset v oltage cancellation mode select 0: comparator mode 1: input offset v oltage cancellation mode bit 6 cbrs : over current protection comparator offset v oltage cancellation reference input select 0: comparator negative input selected 1: comparator positive input selected bit 5~0 cbof5~cbof0 : over current protection comparator input v oltage offset cancellation rev. 1.10 104 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 10? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ocvpr5 register bit 7 6 5 4 3 2 1 0 name ax cbx cax r/w r r r por x x x x: ? nknown bit 7~3 unimplemented, read as 0. bit 2 ax : over current protection operational amplifer digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 1 cbx : over current protection comparator digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 0 cax : over v oltage protection comparator digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage l ocp operational amplifer offset cancellation function opa allows for a commode mode adjustment method of its input offset voltage. ars aofm s1 s2 s3 0 0 on on off 0 1 off on on 1 0 on on off 1 1 on off on the calibration steps are as following: ? set aofm= 1 to setup the offset cancellation mode, here s3 is closed ? set ars to select which input pin is to be used as the reference voltage C s1 or s2 is closed ? adjust aof0~aof5 until the output status changes ? set aofm= 0 to restore the normal opa mode rev. 1.10 104 ?an?a?? 1?? ?01? rev. 1.10 10 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ocp comparator offset cancellation function cmp allows for a commode mode adjustment method of its input offset voltage. cars caofm s1 s2 s3 0 0 on on off 0 1 off on on 1 0 on on off 1 1 on off on the calibration steps are as following: ? set caofm= 1 to setup the offset cancellation mode, here s3 is closed ? set cars to select which input pin is to be used as the reference voltage C s1 or s2 is closed ? adjust caof0~caof5 until the output status changes ? set caofm= 0 to restore the normal comparator a mode ovp comparator offset cancellation function cmp allows for a commode mode adjustment method of its input offset voltage. cbrs cbofm s1 s2 s3 0 0 on on off 0 1 off on on 1 0 on on off 1 1 on off on the calibration steps are as following: ? set cbofm= 1 to setup the offset cancellation mode, here s3 is closed ? set cbrs to select which input pin is to be used as the reference voltage C s1 or s2 is closed ? adjust cbof0~cbof5 until the output status changes ? set cbofm= 0 to restore the normal comparator b mode rev. 1.10 106 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 107 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt a nd i nternal i nterrupts f unctions. t he e xternal i nterrupt i s g enerated b y t he a ction o f the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, comparator, t ime base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a s eries of regis ters, located in the s pecial p urpose d ata m emory, as s hown in the a ccompanying t able. t he re gisters fa ll i nto t hree c ategories. t he fi rst i s t he int c0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi intn pin intne intnf n= 0 o ? 1 ovp ovpe ovpf ocp ocpe ocpf a/d conve ? te ? ade adf m ? lti-f ? nction mfne mfnf n= 0~ ? time base tbne tbnf n= 0 o ? 1 lvd lve lvf eeprom dee def tm tnpe tnpf n= 0 o ? 1 tnae tnaf interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int1s1 int1s0 int0s1 int0s0 intc0 int0f ocpf ovpf int0e ocpe ovpe emi intc1 adf mf ? f mf1f mf0f ade mf ? e mf1e mf0e intc ? int1f tb1f tb0f int1e tb1e tb0e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi ? def lvf dee lve rev. 1.10 106 ?an?a?? 1?? ?01? rev. 1.10 107 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 4 unimplemented, read as "0" b it 3 ~ 2 : defnes int1 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt b it 1 ~ 0 : defnes int0 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 name int0f ocpf ovpf int0e ocpe ovpe emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 b it 7 unimplemented, read as "0" b it 6 : int0 interrupt request flag 0: no request 1: interrupt request b it 5 : over current protection interrupt request fag 0: no request 1: interrupt request b it 4 : over voltage protection interrupt request fag 0: no request 1: interrupt request b it 3 : int0 interrupt control 0: disable 1: enable b it 2 : over current protection interrupt control 0: disable 1: enable b it 1 : over voltage protection interrupt control 0: disable 1: enable b it 0 : global interrupt control 0: disable 1: enable rev. 1.10 108 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 109 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu intc1 register bit 7 6 5 4 3 2 1 0 name adf mf ? f mf1f mf0f ade mf ? e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7 : a/d converter interrupt request flag 0: no request 1: interrupt request b it 6 : multi-function interrupt 2 request flag 0: no request 1: interrupt request b it 5 : multi-function interrupt 1 request flag 0: no request 1: interrupt request b it 4 : multi-function interrupt 0 request flag 0: no request 1: interrupt request b it 3 : a/d converter interrupt control 0: disable 1: enable b it 2 : multi-function interrupt 2 control 0: disable 1: enable b it 1 : multi-function interrupt 1 control 0: disable 1: enable b it 0 : multi-function interrupt 0 control 0: cisable 1: enable rev. 1.10 108 ?an?a?? 1?? ?01? rev. 1.10 109 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu intc2 register bit 7 6 5 4 3 2 1 0 name int1f tb1f tb0f int1e tb1e tb0e r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 unimplemented, read as "0" b it 6 : int 1 interrupt request flag 0: no request 1: interrupt request b it 5 : t ime base 1 interrupt request flag 0: no request 1: interrupt request b it 4 : t ime base 0 interrupt request flag 0: no request 1: interrupt request b it 3 unimplemented, read as "0" b it 2 : int1 interrupt control 0: disable 1: enable b it 1 : t ime base 1 interrupt control 0: disable 1: enable b it 0 : t ime base 0 interrupt control 0: disable 1: enable rev. 1.10 110 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 111 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as "0" b it 5 : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as "0" b it 1 : tm0 comparator a match interrupt control 0: disable 1: enable b it 0 : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 b it 7~6 unimplemented, read as "0" b it 5 : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request b it 4 : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request b it 3 ~2 unimplemented, read as "0" b it 1 : tm1 comparator a match interrupt control 0: disable 1: enable b it 0 : tm1 comparator p match interrupt control 0: disable 1: enable rev. 1.10 110 ?an?a?? 1?? ?01? rev. 1.10 111 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu mfi2 register bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 ~ 6 unimplemented, read as "0" b it 5 : data eeprom interrupt request fag 0: no request 1: interrupt request b it 4 : lvd interrupt request fag 0: no request 1: interrupt request b it 3 ~ 2 unimplemented, read as "0" b it 1 : data eeprom interrupt control 0: disable 1: enable b it 0 : lvd interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter addres s from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. 04h 08h 14h 18h 20h 1c h 24h reques t flag s enabl e bits emi auto disabled in is r interrupts contained wi thin mult i- function interrupt s interrupt na me xxf le gend requ est flag ? no au to reset in is r xxf requ est flag ?a uto reset in is r xxe enable bit xxf le gend ? xxf xxe em i 28h lv f lv d lv e def eeprom dee em i em i em i em i em i em i em i t1 af t m1 a t1 ae t1 pf tm 1 p t1 pe t0 af t m0 a t0 ae t0 pf t m0 p t0 pe ovpf over voltage protection ovpe ocpf over current protection ocpe adf a/d ade em i em i int0f int0 pin int0e 0c h 10h low prio ri ty high vector reques t flag s enabl e bits maste r enabl e interrupt na me mf0f m.funct. 0 mf0e mf1f m.funct. 1 mf1e mf2f m.funct. 2 mf2e tb 0f ti me base 0 tb 0e tb 1f ti me base 1 tb 1e int1 f int1 pi n int1 e interrupt structure rev. 1.10 11 ? ?an?a?? 1?? ?01? rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu external interrupt the external interrupts are controlled by s ignal transitions on the pins in t0, in t1. a n external interrupt reques t w ill take place w hen the external interrupt reques t fags, in t0f, in t1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e, int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f , int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ re gister i s use d t o se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a choice of ei ther risi ng or fall ing or both edge types ca n be chosen to tri gger an ext ernal int errupt. note that the integ register can also be used to disable the external interrupt function. ovp interrupt an ovp interrupt request will take place when the over v oltage protection interrupt request fag, ovpf, is set, which occurs when the over v oltage protection function detects an over voltage condition. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, emi, and over v oltage protection interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an over voltage condition occurs, a subroutine call to the ovp interrupt vector , will take place. when the over v oltage protection interrupt is serviced, the emi bit wi ll be a utomatically cl eared t o disabl e othe r i nterrupts a nd the i nterrupt reque st fa g will be also automatically cleared. ocp interrupt an ocp interrupt request will take place when the over current protection interrupt request fag, ocpf, i s se t, wh ich o ccurs wh en t he ov er c urrent pr otection f unction d etects a n o ver c urrent condition. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, emi, and over current protection interrupt enabl e bit, must frst be set. when the interrupt is enabled, the stack is not full and an over current condition occurs, a subroutine call to the ocp interrupt vector , will take place. when the over current protection interrupt is serviced, the emi bit wi ll be a utomatically cl eared t o disabl e othe r i nterrupts a nd the i nterrupt reque st fa g will be also automatically cleared. rev. 1.10 114 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 11 ? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu multi-function interrupt within th is device there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf 0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request flags from the original source of the multi- function interrupts, namely the tm interrupts, l vd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. rev. 1.10 114 ?an?a?? 1?? ?01? rev. 1.10 11 ? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 b it 7 : tb0 and tb1 control bit 0: disable 1: enable b it 6 : select f tb clock 0: f tbc 1: f sys /4 b it 5 ~ 4 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb b it 3 unimplemented, read as "0" b it 2 ~ 0 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb time base interrupt rev. 1.10 116 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 117 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector a ddress, t he gl obal i nterrupt e nable bi t, e mi, a nd e eprom int errupt e nable bi t, de e, and ass ociated multi-function interrupt enable bit , mf2e, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the emi bit will be automatica lly cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin the mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low voltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit , mf2e, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared . as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the standard t ype tm has two interrupts while the periodic t ype tm also has two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for the standard and periodic type tms there are two interrupt request flags tnpf and tnaf and two enable bits tnpe and tnae. a tm inte rrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit , mfnf (mf0f or mf1f), must frst be set. when the interrupt is enabl ed, the stack is not full and a tm comparator match situati on occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to dis able other interrupts , however only the related m fnf fag (m f0f or m f1f) w ill be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. rev. 1.10 116 ?an?a?? 1?? ?01? rev. 1.10 117 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf 2 f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. rev. 1.10 118 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 119 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu low voltage detector C lvd the device has a low v oltage detector function, also known as l vd. this enable s the device to monitor the power supply voltage, v dd , and provide s a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of fve fxed voltages below which a low volta ge condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 b it 7 ~ 6 unimplemented, read as "0" b it 5 : lvd output flag 0: no low voltage detect 1: low voltage detect b it 4 : low v oltage detector control 0: disable 1: enable b it 3 unimplemented, read as "0" b it 2~0 : select lvd v oltage 000~010: reserved 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v rev. 1.10 118 ?an?a?? 1?? ?01? rev. 1.10 119 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.7v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will remain active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. rev. 1.10 1 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?1 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu application circuits usb i/p 8.4v battery + 50 m ? an ocp io vcc outh outl 50 m ? ovp io io an io HT45FH4M io io io io vss usb o/p io an dapwr/vref rt1 50k/25 51k tl431b 1k 105 104 105 vdd t io 2.5v v5 vdd rev. 1.10 1?0 ?an?a?? 1?? ?01? rev. 1.10 1 ? 1 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.10 1?? ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0 ~ 7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] addm a ? [m] add a ? x adc a ? [m] adcm a ? [m] sub a ? x sub a ? [m] subm a ? [m] sbc a ? [m] sbcm a ? [m] daa [m] add data memo ?? to acc add acc to data memo ?? add immediate data to acc add data memo ?? to acc with ca ??? add acc to data memo ?? with ca ??? s ? bt ? act immediate data f ? om the acc s ? bt ? act data memo ?? f ? om acc s ? bt ? act data memo ?? f ? om acc with ? es ? lt in data memo ?? s ? bt ? act data memo ?? f ? om acc with ca ??? s ? bt ? act data memo ?? f ? om acc with ca ???? ? es ? lt in data memo ?? decimal adj ? st acc fo ? addition with ? es ? lt in data memo ?? 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov c logic operation and a ? [m] or a ? [m] xor a ? [m] andm a ? [m] orm a ? [m] xorm a ? [m] and a ? x or a ? x xor a ? x cpl [m] cpla [m] logical and data memo ?? to acc logical or data memo ?? to acc logical xor data memo ?? to acc logical and acc to data memo ?? logical or acc to data memo ?? logical xor acc to data memo ?? logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memo ?? complement data memo ?? with ? es ? lt in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] inc ? ement data memo ?? with ? es ? lt in acc inc ? ement data memo ?? dec ? ement data memo ?? with ? es ? lt in acc dec ? ement data memo ?? 1 1 note 1 1note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memo ?? ? ight with ? es ? lt in acc rotate data memo ?? ? ight rotate data memo ?? ? ight th ? o ? gh ca ??? with ? es ? lt in acc rotate data memo ?? ? ight th ? o ? gh ca ??? rotate data memo ?? left with ? es ? lt in acc rotate data memo ?? left rotate data memo ?? left th ? o ? gh ca ??? with ? es ? lt in acc rotate data memo ?? left th ? o ? gh ca ??? 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a ? [m] mov [m] ? a mov a ? x move data memo ?? to acc move acc to data memo ?? move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clea ? bit of data memo ?? set bit of data memo ?? 1 note 1 note none none rev. 1.10 1 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu mnemonic description cycles flag affected branch ? mp add ? sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call add ? ret ret a ? x reti ?? mp ? nconditionall ? skip if data memo ?? is ze ? o skip if data memo ?? is ze ? o with data movement to acc skip if bit i of data memo ?? is ze ? o skip if bit i of data memo ?? is not ze ? o skip if inc ? ement data memo ?? is ze ? o skip if dec ? ement data memo ?? is ze ? o skip if inc ? ement data memo ?? is ze ? o with ? es ? lt in acc skip if dec ? ement data memo ?? is ze ? o with ? es ? lt in acc s ? b ? o ? tine call ret ?? n f ? om s ? b ? o ? tine ret ?? n f ? om s ? b ? o ? tine and load immediate data to acc ret ?? n f ? om inte ??? pt ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table to tblh and data memo ?? read table (last page) to tblh and data memo ?? ? note ? note none none miscellaneous nop clr [m] set [m] clr wdt swap [m] swapa [m] halt no ope ? ation clea ? data memo ?? set data memo ?? clea ? watchdog time ? swap nibbles of data memo ?? swap nibbles of data memo ?? with ? es ? lt in acc ente ? powe ? down mode 1 1 note 1 note 1 1 note 1 1 none none none to ? pdf none none to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. rev. 1.10 1?4 ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.10 1 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z rev. 1.10 1?6 ?an?a?? 1?? ?01? rev. 1.10 1 ? 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.10 1 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?9 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none rev. 1.10 1?8 ?an?a?? 1?? ?01? rev. 1.10 1 ? 9 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 [ m].0 affected f ag(s) none rev. 1.10 1 ? 0 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?1 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m] = 0 affected f ag(s) none rev. 1.10 1?0 ?an?a?? 1?? ?01? rev. 1.10 1 ? 1 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc = 0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m] = 0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc = 0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7 ~ [ m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3 ~ a cc.0 [ m].7 ~ [ m].4 acc.7 ~ a cc.4 [ m].3 ~ [ m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] = 0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m] = 0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i = 0 affected f ag(s) none rev. 1.10 1?? ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu tabrd [m] read ta ble to t blh a nd d ata m emory description the p rogram c ode a ddressed b y t he t able p ointer ( tbhp a nd t blp) is m oved t o t he sp ecifed data m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.10 1 ? 4 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?? ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 9 ? 0.419 b 0. ?? 6 0. ? 00 c 0.01 ? 0.0 ? 0 c' 0.496 0. ? 1 ? d 0.104 e 0.0 ? 0 f 0.004 0.01 ? g 0.016 0.0 ? 0 h 0.008 0.01 ? 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6. ? 0 7.6 ? c 0. ? 0 0. ? 1 c' 1 ? .60 1 ? .00 d ? .64 e 1. ? 7 f 0.10 0. ? 0 g 0.41 1. ? 7 h 0. ? 0 0. ?? 0 8 rev. 1.10 1?4 ?an?a?? 1?? ?01? rev. 1.10 1 ?? ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.1 ? 0 0.1 ? 8 c 0.008 0.01 ? c' 0. ??? 0. ? 47 d 0.049 0.06 ? e 0.0 ?? f 0.004 0.010 g 0.01 ? 0.0 ? 0 h 0.007 0.010 0o 8o symbol dimensions in mm min. nom. max. a ? .79 6. ? 0 b ? .81 4.01 c 0. ? 0 0. ? 0 c' 8. ? 1 8.81 d 1. ? 4 1.6 ? e 0.64 f 0.10 0. ?? g 0. ? 8 1. ? 7 h 0.18 0. ?? 0o 8o rev. 1.10 1 ? 6 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 1?7 ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu reel dimensions 20-pin sop (300mil) s ? mbol description dimensions in mm a reel o ? te ? diamete ? ?? 0.01.0 b reel inne ? diamete ? 100.01. ? c spindle hole diamete ? 1 ? .0 +0. ? /-0. ? d ke ? slit width ? .00. ? t1 space between flang ? 4.8 +0. ? /-0. ? t ? reel thickness ? 0. ? 0. ? 20-pin ssop (150mil) s ? mbol description dimensions in mm a reel o ? te ? diamete ? ?? 0.01.0 b reel inne ? diamete ? 100.01. ? c spindle hole diamete ? 1 ? .0 +0. ? /-0. ? d ke ? slit width ? .00. ? t1 space between flang 16.8 +0. ? /-0. ? t ? reel thickness ?? . ? 0. ? rev. 1.10 1?6 ?an?a?? 1?? ?01? rev. 1.10 1 ? 7 ? an ? a ?? 1 ?? ? 01 ? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu carrier tape dimensions 20-pin sop (300mil) symbol description dimensions in mm w ca ?? ie ? tape width ? 4.0 +0. ? /-0.1 p cavit ? pitch 1 ? .00.1 e pe ? fo ? ation position 1.7 ? 0.10 f cavit ? to pe ? fo ? ation(width di ? ection) 11. ? 0.1 d pe ? fo ? ation diamete ? 1. ? 0 +0.10/-0.00 d1 cavit ? hole diamete ? 1. ? 0 +0. ?? /-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 10.80.1 b0 cavit ? width 1 ? . ? 0.1 k0 cavit ? depth ? . ? 0.1 t ca ?? ie ? tape thickness 0. ? 00.0 ? c cove ? tape width ? 1. ? 0.1 20-pin ssop (150mil) symbol description dimensions in mm w ca ?? ie ? tape width 16.0 +0. ? /-0.1 p cavit ? pitch 8.00.1 e pe ? fo ? ation position 1.7 ? 0.10 f cavit ? to pe ? fo ? ation(width di ? ection) 7. ? 0.1 d pe ? fo ? ation diamete ? 1. ? 0 +0.10/-0.00 d1 cavit ? hole diamete ? 1. ? 0 +0. ?? /-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavit ? to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavit ? length 6. ? 0.1 b0 cavit ? width 9.00.1 k0 cavit ? depth ? . ? 0.1 t ca ?? ie ? tape thickness 0. ? 00.0 ? c cove ? tape width 1 ? . ? 0.1 rev. 1.10 1 ? 8 ? an ? a ?? 1 ?? ? 01 ? rev. 1.10 pb ?an?a?? 1?? ?01? HT45FH4M lithium battery backup power assp mcu HT45FH4M lithium battery backup power assp mcu holtek semiconductor inc. (headquarters) no. ?? c ? eation rd. ii ? science pa ? k ? hsinch ?? taiwan tel: 886- ? - ? 6 ? -1999 fax: 886- ? - ? 6 ? -1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f- ?? no. ? - ?? y ? anq ? st. ? nankang softwa ? e pa ? k ? taipei 11 ?? taiwan tel: 886- ? - ? 6 ?? -7070 fax: 886- ? - ? 6 ?? -7 ? 7 ? fax: 886- ? - ? 6 ?? -7 ? 8 ? (inte ? national sales hotline) holtek semiconductor (china) inc. b ? ilding no.10 ? xinzh ? co ?? t ? (no.1 headq ? a ? te ? s) ? 4 c ? izh ? road ? songshan lake ? dongg ? an ? china ??? 808 tel: 86-769- ? 6 ? 6-1 ? 00 fax: 86-769- ? 6 ? 6-1 ? 11 ? 86-769- ? 6 ? 6-1 ??? holtek semiconductor (usa), inc. (north america sales offce) 467 ? 9 f ? emont blvd. ? f ? emont ? ca 94 ?? 8 ? usa tel: 1- ? 10- ??? -9880 fax: 1- ? 10- ??? -988 ? http://www.holtek.com cop ?? ight ? ? 01 ? b ? holtek semiconductor inc. the info ? mation appea ? ing in this data sheet is believed to be acc ?? ate at the time of p ? blication. howeve ?? holt ek ass ? mes no ? es ponsibilit ? a ? ising f ? om t he ? se of the specifications desc ? ibed. the applications mentioned he ? ein a ? e ? sed solel ? fo ? the p ?? pose of ill ? st ? ation and holtek makes no wa ?? ant ? o ? ? ep ? esentation that s ? ch applications will be s ? itable witho ? t f ?? the ? modification ? no ? ? ecommends the ? se of its p ? od ? cts fo ? application that ma ? p ? esent a ? isk to h ? man life d ? e to malf ? nction o ? othe ? wise. holtek's p ? od ? cts a ? e not a ? tho ? ized fo ? ? se as c ? itical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most ? p-to-date info ? mation ? please visit o ?? web site at http://www.holtek.com.tw . |
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